Patents by Inventor Frank Truong
Frank Truong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855125Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.Type: GrantFiled: September 4, 2019Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Srinivas Pietambaram, Brandon C. Marin, Jeremy Ecton, Hiroki Tanaka, Frank Truong
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Publication number: 20230345621Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Applicant: Intel CorporationInventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
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Patent number: 11737208Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.Type: GrantFiled: February 6, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
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Patent number: 11728265Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.Type: GrantFiled: September 12, 2018Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian, Dilan Seneviratne, Yonggang Li, Sameer Paital, Darko Grujicic, Rengarajan Shanmugam, Melissa Wette, Srinivas Pietambaram
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Patent number: 11728077Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.Type: GrantFiled: September 23, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian
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Patent number: 11688692Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.Type: GrantFiled: December 1, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
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Publication number: 20230187331Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Bainye Francoise ANGOUA, Chelsea GROVES, Frank TRUONG, Praneeth AKKINEPALLY, Whitney BRYKS
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Patent number: 11574874Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: GrantFiled: March 30, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong, Praneeth Akkinepally, Andrew J. Brown, Lauren A. Link, Prithwish Chatterjee
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Patent number: 11571876Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.Type: GrantFiled: March 17, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Praneeth Akkinepally, Frank Truong, Dilan Seneviratne
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Patent number: 11462432Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.Type: GrantFiled: March 15, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Frank Truong, Praneeth Akkinepally, Chelsea M. Groves, Whitney M. Bryks, Jason M. Gamba, Brandon C. Marin
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Patent number: 11348865Abstract: A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.Type: GrantFiled: September 30, 2019Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
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Patent number: 11296186Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.Type: GrantFiled: January 8, 2020Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
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Publication number: 20220093515Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
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Patent number: 11276634Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.Type: GrantFiled: May 23, 2017Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Rahul N. Manepalli, David Unruh, Frank Truong, Kyu Oh Lee, Junnan Zhao, Sri Chaitra Jyotsna Chavali
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Patent number: 11233009Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.Type: GrantFiled: March 27, 2020Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
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Publication number: 20220005638Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.Type: ApplicationFiled: September 23, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian
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Patent number: 11158444Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.Type: GrantFiled: February 12, 2018Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian
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Publication number: 20210305163Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
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Publication number: 20210134727Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: ApplicationFiled: March 30, 2017Publication date: May 6, 2021Inventors: Robert A. May, Sri Ranga Sai BOYAPATI, Kristof DARMAWIKARTA, Hiroki TANAKA, Srinivas V. PIETAMBARAM, Frank TRUONG, Praneeth AKKINEPALLY, Andrew J. BROWN, Lauren A. LINK, Prithwish CHATTERJEE
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Publication number: 20210098356Abstract: A substrate for an electronic device may include a first layer defining a first exterior surface of the substrate. The substrate may include a second layer defining a second exterior surface. The first layer and the second layer may include one or more sets of interconnects. The substrate may include one or more interconnect pockets, for instance in the second layer. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. Individual ones of the second set of interconnects may be located within respective individual ones of the interconnect pockets in the second layer. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Praneeth Akkinepally, Jieying Kong, Frank Truong