Abstract: By performing optical measurements and evaluating the optical response of an appropriately prepared measurement site, stress-related characteristics, such as intrinsic stress of dielectric layers, may be evaluated due to the dependency of the optical response on stress-induced modifications of the charge carrier mobility of a conductive layer provided below the dielectric layer probed by an optical signal. Consequently, inline measurement results may be obtained in a highly efficient manner, thereby providing the potential for monitoring complex stress engineering strategies during a manufacturing sequence for forming microstructure devices.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract: A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.

Abstract: A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.

Abstract: A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional three-dimensional transistor architectures. The double channel three-dimensional transistors may be used for forming a static RAM cell with a reduced number of transistors, while also providing scalability by taking advantage of the enhanced controllability of FinFETS and nano pipe transistor architectures.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract: By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level.

Abstract: A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

Abstract: By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.

Abstract: By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract: A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed.

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract: A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.