Abstract: The sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts provide sub-micron devices and processes for manufacturing them with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG which avoids all oxidation steps that could be detrimental in this contact size range. An optional alternative includes large contact area enlarging layers of silicide directly beneath each contact.

Abstract: The sub-micron bipolar devices with method for forming sub-micron contacts provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG to avoid all oxidation steps which otherwise might be detrimental to the extremely thin whisker contacts.

Abstract: The sub-micron bipolar devices with method for forming sub-micron contacts provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG to avoid all oxidation steps which otherwise might be detrimental to the extremely thin whisker contacts.

Abstract: The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET.

Abstract: The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET.

Abstract: The invention provides a sub-micron MOS device and process for manufacturing with contacts down to 0.1 microns. It also provides a sub-micron bipolar device and process for manufacturing it with contacts down to 0.1 microns. Further, there is provided a sub-micron bipolar device of a type having emitter, base and collector adjacent each other rather than in surrounding relationship, together with contacts down to 0.1 micron and process for making the same. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and some convert polysilicon to polyoxide, except where protected by nitride buttons over the electrodes to prevent oxidation of the polysilicon therebeneath. One embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG. In the polysilicon oxidized devices, the contacts may be made oversized to compensate for irregularities in processing.

Abstract: The present invention is a CMOS process for forming an N-channel device and a P-channel device on a doped substrate wherein an active region surrounded by field for the N-channel device is delineated to comprise a thin layer of oxide, a layer of nitride and a further layer of oxide. An active region surrounded by field for the P-channel device is delineated to comprise a thin layer of oxide and a layer of nitride. A well beneath the P-channel active region and the surrounding field region therefor is implanted. Then, the N-channel field is implanted. The oxide layer is removed from the N-channel active region and field oxide is grown for both channels while the well implant and the field implant are concurrently driven-in. The nitride layers are removed, and sacrificial oxide is grown and removed. Implanting is carried out for threshold adjust. The gate oxide is grown, and the gate electrodes of doped polysilicon are delineated for each channel. An activated source and drain is established for each channel.

Abstract: The present invention is a CMOS process for forming an N-channel device and a P-channel device on a doped substrate wherein an active region surrounded by field for the N-channel device is delineated to comprise a thin layer of oxide, a layer of nitride and a further layer of oxide. An active region surrounded by field of the P-channel device is delineated to comprise a thin layer of oxide and a layer of nitride. A well beneath the P-channel active region and the surrounding field region therefor is implanted. Then, the N-channel field is implanted. The oxide layer is removed from the N-channel active region and field oxide is grown for both channels while the well implant and the field implant are concurrently driven-in. The nitride layers are removed, and sacrificial oxide is grown and removed. Implanting is carried out for threshold adjust. The gate oxide is grown, and the gate electrodes of doped polysilicon are delineated for each channel. An activated source and drain is established for each channel.

Abstract: The invention provides a novel high speed hardened NMOS structure and process for developing the structure. In a first embodiment, the <100> surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no transition from the <100> plane to the <111> plane. In a first embodiment, one of the gate electrode overlaps is avoided, thereby eliminating the sidewalk effect or parasitic device from causing leakage on that side of the channel. The preferred embodiment provides a device with no field oxide extending into the silicon wafer and with no overlap of the gate electrode over the field oxide. This is achieved by causing the gate metal interconnect to proceed linearly along the active region over either the source or drain before it leaves the active region, thereby avoiding the establishing of an extra field in the gate region.

Abstract: The invention provides a novel high speed hardened CMOS structure and process for developing the structure. In a first embodiment, the <100> surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no transition from the <100> plane to the <111> plane. In a first embodiment, one of the gate electrode overlaps is avoided, thereby eliminating the sidewalk effect or parasitic device from causing leakage on that side of the channel. The preferred embodiment provides a device with no field oxide extending into the silicon wafer and with no overlap of the gate electrode over the field oxide. This is achieved by causing the gate metal interconnect to proceed linearly along the active region over either the source or drain before it leaves the active region, thereby avoiding the establishing of an extra field in the gate region.

Abstract: The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.

Abstract: The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

Abstract: The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is achieved by a mask which permits doping of the source and drain regions to comprise FETs for the cells indicative of one state of logic while precluding doping of the source and drain regions to complete the channel in the cells comprising the other state of logic. Also, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells. The process simplifies the number of steps required to manufacture the FETs and non-FETs by simply providing the programming after the basic cells are formed. Such unprogrammed structures may be inventoried and simply programmed i.e.

Abstract: The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having oxidation and etch characteristics permits selective oxidation of desired portions only of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. There results semiconductor devices of minimum geometry with selective interconnection capabilities, affording VLSI circuits having increased density with improved yield and reliability.

Abstract: A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices composed of a variable threshold memory device having a thin silicon dioxide gate insulator in combination with a pair of fixed threshold devices having a thicker silicon dioxide gate insulator arranged with a common silicon nitride layer and common gate electrode. The additional fixed threshold peripheral transistors are fabricated without a silicon nitride layer. In addition, the method contains no processing steps subsequent to the fabrication of the PDS devices which necessitate the application of temperatures in excess of 900.degree. C.