Patents by Inventor Franky Juanda LUMBANTORUAN
Franky Juanda LUMBANTORUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967642Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.Type: GrantFiled: September 3, 2021Date of Patent: April 23, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Tuan-Wei Wang, Franky Juanda Lumbantoruan, Chun-Yang Chen
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Patent number: 11942519Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.Type: GrantFiled: September 1, 2021Date of Patent: March 26, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
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Publication number: 20230299146Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Franky Juanda Lumbantoruan, Chien-Jen Sun, Yi-Wei Lien, Tuan-Wei Wang, Chun-Yang Chen
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Publication number: 20230187505Abstract: A semiconductor structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite blocking layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite blocking layer is on the doped compound semiconductor layer, the composite blocking layer and the barrier layer include the same Group III element, and the atomic percent of the same Group III element in the composite blocking layer increases with the distance from the doped compound semiconductor layer.Type: ApplicationFiled: December 9, 2021Publication date: June 15, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen CHEN, Franky Juanda LUMBANTORUAN, Tuan-Wei WANG, Juin-Yang CHEN
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Publication number: 20230070031Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.Type: ApplicationFiled: September 3, 2021Publication date: March 9, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Tuan-Wei Wang, Franky Juanda Lumbantoruan, Chun-Yang Chen
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Publication number: 20230066042Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
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Patent number: 11387356Abstract: A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an Aly1Ga1-y1N layer, and a second sub-layer that is an Alx1Ga1-x1N layer, wherein y1<x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an Aly2Ga1-y2N layer, and a fourth sub-layer that is an Alx2Ga1-x2N layer, wherein y2<x2. M1 and M2 are positive integers, 0?x1, y1 and y2<1, 0<x2?1, and x1<x2, or x1=x2 and y1<y2.Type: GrantFiled: July 31, 2020Date of Patent: July 12, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
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Patent number: 11316040Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.Type: GrantFiled: September 14, 2020Date of Patent: April 26, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Franky Juanda Lumbantoruan, Chia-Ching Huang, Chih-Yen Chen
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Publication number: 20220085196Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.Type: ApplicationFiled: September 14, 2020Publication date: March 17, 2022Inventors: Franky Juanda Lumbantoruan, Chia-Ching Huang, Chih-Yen Chen
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Publication number: 20220037516Abstract: A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an Aly1Ga1-y1N layer, and a second sub-layer that is an Alx1Ga1-x1N layer, wherein y1<x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an Aly2Ga1-y2N layer, and a fourth sub-layer that is an Alx2Ga1-x2N layer, wherein y2<x2. M1 and M2 are positive integers, 0?x1, y1 and y2<1, 0<x2?1, and x1<x2, or x1=x2 and y1<y2.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen CHEN, Franky Juanda LUMBANTORUAN
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Publication number: 20220029007Abstract: A semiconductor structure and a semiconductor device are provided. The semiconductor includes a substrate, a seed layer on the substrate, a buffer layer on the seed layer, a back barrier layer with a V-group element polarity on the buffer layer, a channel layer on the back barrier layer, and a front barrier layer on the channel layer.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Yen CHEN, Franky Juanda LUMBANTORUAN