Abstract: A monolithic transmitter photonic integrated circuit (TxPIC) chip comprises an array of modulated sources formed on the PIC chip and having different operating wavelengths according to a standardized wavelength grid and providing signal outputs of different wavelengths. Pluralities of wavelength tuning elements are integrated on the chip, one associated with each of the modulated sources. An optical combiner is formed on the PIC chip and the signal outputs of the modulated sources are optically coupled to one or more inputs of the optical combiner and provided as a combined channel signal output from the combiner. The wavelength tuning elements provide for tuning the operating wavelength of the respective modulated sources to be approximate or to be chirped to the standardized wavelength grid. The wavelength tuning elements are temperature changing elements, current and voltage changing elements or bandgap changing elements.

Abstract: A method of operating an array of laser sources integrated as an array in a single monolithic chip where the steps include designing the laser sources to have different target emission wavelengths so that together they form a spectral emission wavelength grid, coupling outputs from the laser sources to an array of gain/loss elements also integrated on the single monolithic chip, one each receiving the output from a respective laser source; and adjusting the outputs with the gain/loss elements so that the power levels across the laser source array are substantially uniform.

Abstract: An optical probe and a method for testing an optical chip or device, such as an photonic integrated circuit (PIC), to provide for testing of such devices or circuits while they are still in their in-wafer form and is accomplished by using a an optical probe for interrogation of the circuit where an access is provided in the wafer to one or more of such in-wafer devices or circuits. As one example, the interrogation may be an interrogation beam provided at the access input to the in-wafer device or circuit. As another example, the interrogation may be an optical pickup from the access input to the in-wafer device or circuit.

Abstract: A photonic integrated circuit (PIC) comprises a plurality of integrated optically coupled components formed in a surface of the PIC and a passivating layer overlies at least a portion of the PIC surface. The overlying passivating layer comprises a material selected from the group consisting of BCB, ZnS and ZnSe. Also, when the circuits are PIC chips are die in the semiconductor wafer, a plurality of linear cleave streets are formed in a wafer passivation layer where a pattern of the cleave streets define separate PIC chips in the wafer for their subsequent singulation from the wafer.

Abstract: The Group III–V quaternary, InAlGaAs is employed as a waveguide layer in optical components, such as In-P based array waveguide gratings (AWGs), avalanche photodiodes (APDs) or other optical components that contain a waveguide core in the InP regime. The deployment of InAlGaAs waveguides provides for high uniform photoluminescent (PL) emission wavelength across the wafer for InAlGaAs waveguides as compared to InGaAsP waveguides as now commonly employed in such optical devices or components. The use of an InAlGaAs waveguide core has particular utility when deployed in a photonic integrated circuit (PIC) such as an AWG with a plurality of outputs optically integrated with a plurality of photodetectors, such as APDs which are exemplified in this disclosure. In lieu of an InAlGaAs waveguide, combination layers of InGaAs/InAlAs, InGaAs/InAlGaAs or InAlAs/InAlGaAs may be employed or stacks of such layers to form the waveguides in the PIC chip.

Abstract: An InP-based photonic integrated circuit (PIC) includes an optical passive element in the circuit with no bias current applied to such an element. A passivation cladding layer overlies a surface of the optical passive element where the passivation layer comprises benzocyclobutene polymer or BCB.

Abstract: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that it monotonically increases in thickness through the transition region to the free space coupler region.

Abstract: A monolithic photonic integrated circuit (PIC) chip comprises an array of modulated sources providing a plurality of channel signals of different wavelengths and an optical combiner coupled to receive the channel signals and produce a combined output of the channel signals. The arrays of modulated sources are formed as ridge waveguides to enhance the output power from the respective modulated sources so that the average output power from the sources is approximately 2 to 4 times higher than in the case of comparable arrays of modulated sources formed as buried waveguides.

Abstract: An optical transport network comprises a monolithic transmitter photonic integrated circuit (TxPIC) InP-based chip and a monolithic receiver photonic integrated circuit (RxPIC) InP-based chip.

Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data.

Abstract: A method for forming and apparatus comprising a free space coupler region having a plurality of optical waveguides coupled to the space coupler region at an interface region, the waveguides converging with one another to the interface region, and a trench formed between adjacent waveguides, the depth of the trench or trenches extending from an outer point to the interface region and monotonically decreasing in depth from the outer point to the interface region.

Abstract: An arrayed waveguide grating (AWG) comprises at least two free space regions, a plurality of grating arms extending between the two space regions, a passivation layer formed over the arrayed waveguide grating and a plurality of inputs at least to one of the free space regions to receive a plurality of channel signals separated by a predetermined channel spacing. A depth of the passivation layer chosen by providing a TE to TM wavelength shift between TE and TM modes propagating through the arrayed waveguide grating being approximately less than or equal to 20% of a magnitude of the channel spacing.

Abstract: Disclosed are apparatus and methods of reducing insertion loss, passivation, planarization and in-wafer testing of integrated optical components and in-wafer chips in photonic integrated circuits (PICs).

Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data.

Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.

Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III-V layer comprises InAlAs:O or InAlAs:O:Fe.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: A III-nitride light-emitting structure including a p-type layer, an n-type layer, and a light emitting layer is grown on a growth substrate. The III-nitride light-emitting structure is wafer bonded to a host substrate, then the growth substrate is removed. In some embodiments, a first electrical contact and first bonding layer are formed on the III-nitride light-emitting structure. A second bonding layer is formed on the host substrate. In such embodiments, wafer bonding the III-nitride light emitting structure to the host substrate comprises bonding the first bonding layer to the second bonding layer. After the growth substrate is removed, a second electrical contact may be formed on a side of the III-nitride light-emitting device exposed by removal of the growth substrate.

Abstract: A solderable light-emitting diode (LED) chip and a method of fabricating an LED lamp embodying the LED chip utilize a diffusion barrier that appreciably blocks molecular migration between two different layers of the LED chip during high temperature processes. In the preferred embodiment, the two different layers of the LED chip are a back reflector and a solder layer. The prevention of intermixing of the materials in the back reflector and the solder layer impedes degradation of the back reflector with respect to its ability to reflect light emitted by the LED. The LED chip includes a high power AlInGaP LED or other type of LED, a back reflector, a diffusion barrier and a solder layer. Preferably, the back reflector is composed of silver (Ag) or Ag alloy and the solder layer is made of indium (In), lead (Pb), gold (Au), tin (Sn), or their alloy and eutectics. In a first embodiment, the diffusion layer is made of nickel (Ni) or nickel-vanadium (NiV).

Abstract: The invention is a method for designing semiconductor light emitting devices such that the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.