Abstract: The present invention operates within a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing system. This RAM, termed the MCRAM, is used to store the timing information for memory operations. In particular, the MCRAM stores for each of the memory operations, Read, Write, and Refresh, the relevant information for RAS, CAS, LD, and AD timing signals. The presently preferred embodiment of the invention contemplates a particular programming process wherein the MCRAM is initially loaded with generic timing information which is acceptable to all possible DRAM memory modules. Following this loading operation, the processor obtains the ID number of the DRAMs within a particular memory module. This ID number is used in a look-up table to obtain the vendor-specific optimal timing for DRAMs corresponding to this ID number. The processor then writes this optimal timing information into the MCRAM.

Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W.