Abstract: In one embodiment, a vertical MOSFET is formed having a lower gate portion overlying the channel region of the MOSFET and separated from the channel region by a thin gate oxide layer. An upper gate portion is formed overlying the drain of the MOSFET and separated from the drain by a relatively thick oxide layer. In this particular embodiment, since the dielectric thickness between the upper gate portion and the drain is relatively large, the MOSFET exhibits a lower gate-drain capacitance (C.sub.GD) value, while the threshold voltage of the MOSFET remains relatively unchanged. The upper gate portion may be electrically connected to the lower gate portion or may be electrically isolated from the lower gate portion. A preferred method of forming the resulting MOSFET having this lowered C.sub.GD allows the source and body regions to be precisely aligned with the drain edge of the lower gate portion.

Abstract: In one embodiment, a vertical MOSFET is formed having a lower gate portion overlying the channel region of the MOSFET and separated from the channel region by a thin gate oxide layer. An upper gate portion is formed overlying the drain of the MOSFET and separated from the drain by a relatively thick oxide layer. In this particular embodiment, since the dielectric thickness between the upper gate portion and the drain is relatively large, the MOSFET exhibits a lower gate-drain capacitance (C.sub.GD) value, while the threshold voltage of the MOSFET remains relatively unchanged. The upper gate portion may be electrically connected to the lower gate portion or may be electrically isolated from the lower gate portion. A preferred method of forming the resulting MOSFET having this lowered C.sub.GD allows the source and body regions to be precisely aligned with the drain edge of the lower gate portion.

Abstract: An improved FET is described in which a conductive layer connects the source structure to a truncated source extension which underlies an insulative gate layer and connects to a channel region. The conductive layer is of substantially lower resistivity than the source extension, thereby significantly reducing the lateral resistance of the device to diminish losses and reduce the likelihood of a parasitic bipolar transistor turning on. The invention can be implemented in both vertical and lateral devices. For a lateral device the drain is connected by a low resistance conductive layer to the gate region in a manner similar to the source.

Abstract: An improved FET is described in which a conductive layer connects the source structure to a truncated source extension which underlies an insulative gate layer and connects to a channel region. The conductive layer is of substantially lower resistivity than the source extension, thereby significantly reducing the lateral resistance of the device to diminish losses and reduce the likelihood of a parasitic bipolar transistor turning on. The invention can be implemented in both vertical and lateral devices. For a lateral device the drain is connected by a low resistance conductive layer to the gate region in a manner similar to the source.