Abstract: A system is provided for synchronizing a PSTN clock and a DSL clock. The system comprises a PSTN interface for transmitting and receiving voiceband samples, a data DSL transceiver for modulating and demodulating data to and from DSL samples, a synchronization circuit for synchronizing the voiceband samples and the data samples, and a converter for converting the synchronized voiceband and DSL samples between analog and digital formats. The synchronization circuit synchronizes the voiceband and the data samples for conversion by the same converter.

Abstract: A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.

Abstract: A system and method for reducing peak to average power ratio (PAR) in single and multi-carrier transmitters while accounting for the effect of the transmit filters without significantly affecting a requisite transmission Power Spectral Density (PSD) mask. To this end, in a multicarrier communication system, a DSL transmitter is provided that transmits a multicarrier symbol having a controlled peak-to-average power ratio (PAR) and which is a function of a plurality of information signals. The transmitter has a power reducer that reduces the PAR of the multicarrier symbol by modifying a selected information signal of a plurality of information signals, the modified signal including an information component, a peak reduction component, and a transmission channel response component.

Abstract: A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.

Abstract: A system is provided for synchronizing a PSTN clock and a DSL clock. The system comprises a PSTN interface for transmitting and receiving voiceband samples, a data DSL transceiver for modulating and demodulating data to and from DSL samples, a synchronization circuit for synchronizing the voiceband samples and the data samples, and a converter for converting the synchronized voiceband and DSL samples between analog and digital formats. The synchronization circuit synchronizes the voiceband and the data samples for conversion by the same converter.

Abstract: A system and method for reducing peak to average power ratio (PAR) in single and multi-carrier transmitters while accounting for the effect of the transmit filters without significantly affecting a requisite transmission Power Spectral Density (PSD) mask. To this end, in a multicarrier communication system, a DSL transmitter is provided that transmits a multicarrier symbol having a controlled peak-to-average power ratio (PAR) and which is a function of a plurality of information signals. The transmitter has a power reducer that reduces the PAR of the multicarrier symbol by modifying a selected information signal of a plurality of information signals, the modified signal including an information component, a peak reduction component, and a transmission channel response component.