Abstract: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one switch element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A switch element is positioned on or off a memory module and includes two transistors in embodiments of the invention. One or more switch elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical switch topology allows for increasing the number of memory modules to more than two memory modules without adding switch elements serially on each channel. Switch elements allow for increasing the number of ranks of memory modules in a system, while also achieving many of the benefits associated with point-to-point topology.

Abstract: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device and at least one flyby element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A flyby element is positioned on a memory module and/or in the buffer device and includes conductive element or signal line in embodiments of the invention. One or more flyby elements are coupled to one or more memory modules to allow for upgrades of memory modules in a memory system. An asymmetrical flyby topology allows for increasing the number of memory modules to more than two memory modules without increasing any more delay than is present in with two memory modules.

Abstract: A method and apparatus are provided for measuring a bit rate between a client and a server. In an embodiment of the invention, a number of bits included only within one or more transaction units are measured over a time period. The time period is a sum of time durations of each of the transaction units. In an embodiment of the invention, bit rate measurements are performed on a server and in another embodiment of the invention bit rate measurements are performed on a client. Embodiments of the invention include adapting, by the server, of content to be sent to the client based on the bit rate measurements. Embodiments of the invention further include reporting the measured bit rate to the server when the bit rate measurements are performed on the client. Other aspects of the invention include sending an indication of the measured bit rate and a desired bit rate to the server when bit rate measurements are performed in the client.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one switch element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A switch element is positioned on or off a memory module and includes two transistors in embodiments of the invention. One or more switch elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical switch topology allows for increasing the number of memory modules to more than two memory modules without adding switch elements serially on each channel. Switch elements allow for increasing the number of ranks of memory modules in a system, while also achieving many of the benefits associated with point-to-point topology.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device and at least one flyby element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A flyby element is positioned on a memory module and/or in the buffer device and includes conductive element or signal line in embodiments of the invention. One or more flyby elements are coupled to one or more memory modules to allow for upgrades of memory modules in a memory system. An asymmetrical flyby topology allows for increasing the number of memory modules to more than two memory modules without increasing any more delay than is present in with two memory modules.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device and at least one splitter element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A splitter element is positioned on or off a memory module and includes three resistors in embodiments of the invention. Three resistors form a Y or D topology in embodiments of the invention. One or more splitter elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical splitter topology allows for increasing the number of memory modules to more than two memory modules without adding splitter elements serially on each channel.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. The configurable width buffer device is coupled to at least one memory device (by way of an internal channel), entry pin and exit pin on the memory module. The configurable width buffer device includes a multiplexer/demultiplexer circuit coupled to the entry pin and the internal channel for accessing the memory device. A bypass circuit is coupled to the entry pin and the exit pin in order to allow information to be transferred through the memory module to another coupled memory module in the memory system by way of an external channel.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Abstract: A method and apparatus are provided for measuring a bit rate between a client and a server. In an embodiment of the invention, a number of bits included only within one or more transaction units are measured over a time period. The time period is a sum of time durations of each of the transaction units. In an embodiment of the invention, bit rate measurements are performed on a server and in another embodiment of the invention bit rate measurements are performed on a client. Embodiments of the invention include adapting, by the server, of content to be sent to the client based on the bit rate measurements. Embodiments of the invention further include reporting the measured bit rate to the server when the bit rate measurements are performed on the client. Other aspects of the invention include sending an indication of the measured bit rate and a desired bit rate to the server when bit rate measurements are performed in the client.

Abstract: The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.