Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.

Abstract: A system and method for an embedded disk controller is provided. The embedded disk controller includes a main processor in communication with a first bus. A second processor communicates with a second bus. An external bus interface controller (“EBC”) located on the embedded disk controller manages a plurality of memory devices external to the system embedded disk controller via an external bus interface and coupled to the first bus and an external bus. Each of the plurality of memory devices has at least one of different timing characteristics and different data widths. The EBC is coupled to the first bus and stores at least one of a segment descriptor register and at least a device range register.

Abstract: An expander coupled between at least a first and second SCSI device for transmitting data and training patterns is provided. The expander includes, a first detection module for detecting a training pattern received from the first device; a second detection module that detects when a first section of the training pattern has been transmitted to the second device; and means for changing the expander's mode from a training mode to a repeat mode after the first section.

Abstract: A system and method for an embedded disk controller is provided with an external bus interface controller (“EBC”) for managing devices external to the system via an external bus interface, wherein the EBC is coupled to a high performance bus and includes at least a segment descriptor register and at least a device range register. The segment descriptor register allows firmware to program timing characteristics of the devices. The device range register enables the first main processor to access an address space in the devices.