Patents by Inventor Frederick Daniel Weber
Frederick Daniel Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10013371Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: November 22, 2016Date of Patent: July 3, 2018Assignee: Google LLCInventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9727458Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.Type: GrantFiled: September 14, 2012Date of Patent: August 8, 2017Assignee: Google Inc.Inventors: David T. Wang, Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, Frederick Daniel Weber
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Patent number: 9632929Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.Type: GrantFiled: February 8, 2007Date of Patent: April 25, 2017Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Publication number: 20170075831Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: ApplicationFiled: November 22, 2016Publication date: March 16, 2017Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9542352Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.Type: GrantFiled: February 8, 2007Date of Patent: January 10, 2017Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9542353Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.Type: GrantFiled: October 30, 2007Date of Patent: January 10, 2017Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9507739Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: October 26, 2015Date of Patent: November 29, 2016Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Publication number: 20160048466Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: ApplicationFiled: October 26, 2015Publication date: February 18, 2016Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9171585Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: GrantFiled: November 26, 2013Date of Patent: October 27, 2015Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastien Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9047976Abstract: A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.Type: GrantFiled: October 26, 2006Date of Patent: June 2, 2015Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8977806Abstract: One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.Type: GrantFiled: September 15, 2012Date of Patent: March 10, 2015Assignee: Google Inc.Inventors: Daniel L. Rosenband, Frederick Daniel Weber, Michael John Sebastian Smith
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Patent number: 8949519Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.Type: GrantFiled: July 22, 2009Date of Patent: February 3, 2015Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8868829Abstract: A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.Type: GrantFiled: February 6, 2012Date of Patent: October 21, 2014Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8797779Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.Type: GrantFiled: September 14, 2012Date of Patent: August 5, 2014Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael J. S. Smith, David T. Wang, Frederick Daniel Weber
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Publication number: 20140192583Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).Type: ApplicationFiled: November 26, 2013Publication date: July 10, 2014Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastien Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8773937Abstract: An apparatus includes multiple first memory circuits, in which the multiple first memory circuits are positioned on at least one dual in-line memory module (DIMM). The apparatus includes an interface circuit operable to interface the first memory circuits with a system; present the first memory circuits to the system as one or more simulated second memory circuits; transmit, in response to receiving a first refresh control signal sent from the system to the one or more simulated memory circuits, multiple second refresh control signals to the first memory circuits; and apply a respective delay to each second refresh control signal transmitted to a corresponding first memory circuit. Each simulated second memory circuit has a corresponding second memory capacity that is greater than a first memory capacity of at least one of the first memory circuits.Type: GrantFiled: December 9, 2011Date of Patent: July 8, 2014Assignee: Google Inc.Inventors: Keith R. Schakel, Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8745321Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.Type: GrantFiled: September 14, 2012Date of Patent: June 3, 2014Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8671244Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.Type: GrantFiled: July 13, 2011Date of Patent: March 11, 2014Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8667312Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.Type: GrantFiled: May 14, 2012Date of Patent: March 4, 2014Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 8601204Abstract: A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.Type: GrantFiled: July 13, 2011Date of Patent: December 3, 2013Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber