Abstract: A fault tolerant memory system including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location has a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of the memory chips or a previously assigned spare chip in the event that a chip failure is identified. A memory maintenance facility for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.

Abstract: A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages.

Abstract: A memory organization having one or more groups of memory arrays is disclosed. Each array, which may be on a single chip, is provided with both a data port and a separate address port which may also serve as an alternate data port. Use of the alternate data ports permits a substantially smaller number of input/output circuits to be used than the number required if both the address and data ports are used. The standard data port is, however, available should a higher-speed application be desired using separate address and data ports. In a single-port application, an on-chip data buffer permits the data to be sent and received through the address port in timed relationship with row and column address signals and without interfering with such address signals. An optional group select signal permits a large memory organization to utilize the alternate data ports of numerous groups of array chips.

Abstract: A memory organization having one or more groups of memory arrays is disclosed. Each array, which may be on a single chip, is provided with both a data port and a separate address port which may also serve as an alternate data port. Use of the alternate data ports permits a substantially smaller number of input/output circuits to be used than the number required if both the address and data ports are used. The standard data port is, however, available should a higher-speed application be desired using separate address and data ports. In a single-port application, an on-chip data buffer permits the data to be sent and received through the address port in timed relationship with row and column address signals and without interfering with such address signals. An optional group select signal permits a large memory organization to utilize the alternate data ports of numerous groups of array chips.

Abstract: An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.

Abstract: A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.

Abstract: A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

Abstract: A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones.In one embodiment, the circuit comprises means for generating a parity bit, P.sub.k, for each of K data fields in the ECC word; means for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C.sub.j, to form H bits; and means for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non-carry) sum of the syndrome bits to detect syndrome generation path failures.

Abstract: A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

Abstract: Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.

Abstract: Swapping of bits between different words of a memory is accomplished by a single permutation means. The single permutation means generates actual address bits for all the bit positions in a memory word. These actual address bits are in a local store. Each time a memory word is accessing the locations of the bits are substituted for logical address bits and fed to the decoders of the different bit positions in the memory word being accessed.

Abstract: A method of operating a large fault tolerant semiconductor memory is described which increases the probability that data words read from memory will not contain uncorrectable errors. The method involves storing a data word at a location in memory that may have a defect in either the true form or compliment form depending on which form will be perceived by an error correcting system as containing no errors on readout. Each data word transferred to memory is tested to see if one form or the other results in an error on readout. If the true form results in an error indication, the data portion of the word is stored in compliment form and the check byte stored in true form.On a subsequent transfer of the word from memory, the ECC system indicates an apparent uncorrectable error resulting from both portions of the word being stored in a different form while in fact the uncorrectable error indication is a signal that the data portion was stored in compliment form.

Abstract: A recirculating loop memory array is disclosed adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each loop of the array is provided with a shift register stage for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.

Abstract: A CCD recirculating memory system is disclosed in which "partially good" CCD memory chips and "all good" memory chips are mounted on memory cards. The defective portions of the partially good chips are in the same chip octants on the same card. The cards are addressed by address permutation means which causes the defective portions to appear to have the same predetermined address to the operating system.The addressed CCD row on the partially good chips are clocked at a fast rate while the unaddressed rows are clocked at a slow rate. All of the rows of the "all good" chips are clocked at a fast rate when a defective portion of the partially good chips is being addressed and are otherwise clocked at a slow rate.A select signal is generated whenever the predetermined address is invoked and causes the substitution of an all good chip for the addressed partially good chip.

Abstract: Apparatus is disclosed for quickly testing memory arrays of multiple recirculating loop memory elements. All loops are loaded simultaneously with identical test bits in the same time required to load a single loop. The loaded data is verified by means of a comparison gate which ANDs the outputs of all elements and produces a data verification output signal only in the event that all of the data from each element is identical with that from all other elements on a serial bit-by-bit basis.

Abstract: Apparatus is disclosed for quickly testing memory arrays of multiple recirculating loop memory elements and for locating faulty elements, if any, within designated subdivisions of said array. All loops are loaded with identical test bits. The loaded data is verified and faulty elements, if any, are located by means of a plurality of comparison AND gates. Each gate is connected to the output of a respective subdivision of the array elements and produces a first output signal when all such outputs are identical (on a serial bit-by-bit basis) and produces a second output signal when all said outputs are not identical. The output signals from the respective comparison AND gates are sensed in serial succession to locate the array subdivision containing any faulty elements.

Abstract: A computer paging store memory utilizing line addressable random access memories (LARAM) including charge coupled device (CCD) shift registers in which data is read out of the memory for utilization in a block storage memory without loss of refresh time due to the refresh of individual CCD shift registers. The memory is organized as a number of parallel-connected memory storage units, each of which includes a separate interface logic, a refresh control and a number of memory array units, each of which in turn is constructed of LARAM devices, each of which must be refreshed within a predetermined time interval. Data is normally read out from the LARAM devices one at a time in sequence. During the readout operation, a detection is continuously made which determines whether the next LARAM device in sequence must be refreshed during the subsequent readout time period.

Abstract: In an electronic data processing system having a plurality of dynamic memory units associated therewith, the presently disclosed technique simultaneously refreshes a plurality of asynchronously operating memory units providing synchronous availability to the processor. The processor includes means for determining whether any of the memory units will be required by the processor within a time interval required to perform a refresh operation and, if not, then a "force refresh" signal is sent to the memory system to synchronously refresh all the memory units. Each of the dynamic memory units retains its internal refresh scheme to prevent loss of the stored information in the event that a force refresh signal is not received within the retention time of the dynamic memory unit.

Abstract: A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.