Abstract: A fault tolerant memory system is described including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location comprises a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of said memory chips or a previously assigned spare chip in the event that a chip failure is identified. Means for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.

Abstract: A parity checking scheme for detecting memory array word line failures whereby all of the data and parity bits of a plurality of bytes sharing the same word line erroneously assume the value "1" or the value "0". When storing data in the array, the data and parity bits comprising each byte are stored directly except for the parity bit of a selected one of the bytes, which parity bit is inverted by a gated inverter circuit before storing. The same gated inverter circuit also inverts the parity bit of the selected byte upon reading the stored data. All of the remaining bits of all of the remaining bytes are read directly. The read bits of each byte are applied to a respective parity checking circuit of the same even or odd parity type as is used in storing the data. The outputs of all of the parity checking circuits are applied to error control logic.