Patents by Inventor Frederick K.H. Lee
Frederick K.H. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069772Abstract: A storage operation die collision avoidance system includes a storage subsystem providing a first superblock and a second superblock. A storage operation subsystem is coupled to the storage subsystem and performs first storage operations for the first superblock using a first die in the storage subsystem. The storage operation subsystem then determines second storage operations for performance for the second superblock and, without a fixed die storage operation order, identifies a second die in the storage subsystem that is available to perform the second storage operations for the second superblock while at least some of the first storage operations are performed for the first superblock using the first die in the storage subsystem. The storage operation subsystem then performs the second storage operations for the second superblock using the second die in the storage subsystem.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Girish Desai, Frederick K.H. Lee, Dody Suratman
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Patent number: 11847326Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storage operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.Type: GrantFiled: April 27, 2022Date of Patent: December 19, 2023Assignee: Dell Products L.P.Inventors: Girish Desai, Frederick K. H. Lee
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Patent number: 11837306Abstract: A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.Type: GrantFiled: April 23, 2022Date of Patent: December 5, 2023Assignee: Dell Products L.P.Inventors: Frederick K. H. Lee, Robert Proulx, Jie Wu
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Patent number: 11822429Abstract: A storage device RAID data write intermediate parity system includes a storage device coupled to a host system and including a storage subsystem and a volatile memory system. The storage device RAID data write intermediate parity system receives first primary data from the host system, and stores the first primary data in the volatile memory system. The storage device RAID data write intermediate parity system then stores a first subset of the first primary data in the storage system, generates first intermediate parity data using the first subset of the first primary data, stores the first intermediate parity data in the volatile memory system and, in response, erases the first subset of the first primary data from the volatile memory system.Type: GrantFiled: April 8, 2022Date of Patent: November 21, 2023Assignee: Dell Products L.P.Inventors: Girish Desai, Frederick K. H. Lee
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Publication number: 20230350584Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storge operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: Girish Desai, Frederick K.H. Lee
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Publication number: 20230343408Abstract: A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.Type: ApplicationFiled: April 23, 2022Publication date: October 26, 2023Inventors: Frederick K.H. Lee, Robert Proulx, Jie Wu
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Publication number: 20230325278Abstract: A storage device RAID data write intermediate parity system includes a storage device coupled to a host system and including a storage subsystem and a volatile memory system. The storage device RAID data write intermediate parity system receives first primary data from the host system, and stores the first primary data in the volatile memory system. The storage device RAID data write intermediate parity system then stores a first subset of the first primary data in the storage system, generates first intermediate parity data using the first subset of the first primary data, stores the first intermediate parity data in the volatile memory system and, in response, erases the first subset of the first primary data from the volatile memory system.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Inventors: Girish Desai, Frederick K.H. Lee
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Patent number: 11620058Abstract: In general, embodiments of the invention relate tracking the operating temperature of the solid-state memory modules (SSMMs) in order to improve their performance.Type: GrantFiled: July 28, 2021Date of Patent: April 4, 2023Assignee: Dell Products L.P.Inventors: Frederick K. H. Lee, Girish B. Desai, Samuel Hudson, Robert J. Proulx, Michael Rijo, Leland W. Thompson
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Publication number: 20230030620Abstract: In general, embodiments of the invention relate tracking the operating temperature of the solid-state memory modules (SSMMs) in order to improve their performance.Type: ApplicationFiled: July 28, 2021Publication date: February 2, 2023Inventors: Frederick K.H. Lee, Girish B. Desai, Samuel Hudson, Robert J. Proulx, Michael Rijo, Leland W. Thompson
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Patent number: 10564864Abstract: A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.Type: GrantFiled: October 4, 2018Date of Patent: February 18, 2020Assignee: DELL PRODUCTS L.P.Inventors: Justin L. Ha, Frederick K. H. Lee, Seungjune Jeon
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Patent number: 10459635Abstract: Window based mapping is used to reduce the usage of volatile memory for storing the mapping of logical to physical addresses for accesses to data in a flash drive. Two separate mapping tables for translation of logical addresses to physical addresses (L2P), e.g., an L2P front map and an L2P back map, are used where the L2P front map acts as a window to the L2P back map. The L2P front map has smaller granularity for data accesses than the L2P back map. The data accessed using the L2P front map can allow the flash drive to function with relatively same performance as a fully mapped drive with a single mapping table.Type: GrantFiled: January 20, 2017Date of Patent: October 29, 2019Assignee: SK Hynix Inc.Inventors: Matthew Lewis Call, Frederick K. H. Lee, Johnny Lam, Stephen Silva
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Patent number: 10296452Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for determining a pool of blocks from the plurality of blocks as garbage collection (GC) victim block candidates based on a number of valid pages left in each of the plurality of blocks, and selecting a block from the pool of blocks having a minimum number of valid pages as a victim block for garbage collection.Type: GrantFiled: May 11, 2016Date of Patent: May 21, 2019Assignee: SK hynix Inc.Inventors: Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng, Yunhsiang Hsueh
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Patent number: 10275297Abstract: A plurality of bins and a plurality of soft read values are stored in a lookup table where those bins that are either a leftmost bin or a rightmost bin correspond to soft read values having a maximum magnitude. Bin identification information is received for a cell in solid state storage. A soft read value is generated for the cell in solid state storage, including by: accessing the lookup table, mapping the received bin identification information to one of the plurality of bins in the lookup table, and selecting the soft read value in the lookup table that corresponds to the bin which is mapped to.Type: GrantFiled: November 3, 2014Date of Patent: April 30, 2019Assignee: SK hynix memory solutions Inc.Inventors: Frederick K. H. Lee, Jason Bellorado, Marcus Marrow
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Patent number: 10185623Abstract: A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.Type: GrantFiled: April 6, 2016Date of Patent: January 22, 2019Assignee: SK Hynix Memory Solutions Inc.Inventors: Arunkumar Subramanian, Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng, Jason Bellorado
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Patent number: 10127157Abstract: A total bytes written (TBW) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the TBW requirement.Type: GrantFiled: September 2, 2015Date of Patent: November 13, 2018Assignee: SK Hynix Inc.Inventors: Xiangyu Tang, Frederick K. H. Lee
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Patent number: 10102146Abstract: Methods may include after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading an open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the LBA table in the least recently saved section.Type: GrantFiled: March 28, 2016Date of Patent: October 16, 2018Assignee: SK Hynix Inc.Inventors: Shwetashree Virajamangala, Nagabhushan Hegde, Frederick K. H. Lee
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Patent number: 10055168Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.Type: GrantFiled: August 31, 2016Date of Patent: August 21, 2018Assignee: SK Hynix Inc.Inventors: Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng
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Patent number: 9985647Abstract: Methods of encoding a near-symbol balanced (NSB) sequence may include selecting, with a controller, a constraint based on an amount of bits, determining, with the controller, a plurality of sections in a codebook based on permutations defined by the selected constraint, and partitioning, with the controller, a section among the plurality of sections into a plurality of partitions until each of the plurality of partitions include a number of entries equal to or less than a predetermined number of entries.Type: GrantFiled: March 4, 2016Date of Patent: May 29, 2018Assignee: SK Hynix Inc.Inventors: Frederick K. H. Lee, Marcus Marrow
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Patent number: 9842023Abstract: A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value.Type: GrantFiled: January 27, 2016Date of Patent: December 12, 2017Assignee: SK Hynix Memory Solutions Inc.Inventors: Xiangyu Tang, Frederick K. H. Lee, Jason Bellorado, Arunkumar Subramanian, Lingqi Zeng
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Patent number: 9812193Abstract: A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold.Type: GrantFiled: September 9, 2014Date of Patent: November 7, 2017Assignee: SK Hynix Inc.Inventors: Christopher S. Tsang, Frederick K. H. Lee, Xiangyu Tang, Zheng Wu, Jason Bellorado