Abstract: Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

Abstract: A method of making a plug transistor is disclosed. The method includes providing a semiconductor substrate with an active region of a first conductivity type, providing a doped layer of a second conductivity type in the active region, forming a dielectric layer over the active region, forming an opening in the dielectric layer, implanting a dopant of the first conductivity type through the opening into a portion of the doped layer beneath the opening thereby counterdoping the portion of the doped layer and splitting the doped layer into source and drain regions, forming a gate insulator on the active region and in the opening, and forming a gate on the gate insulator and in the opening and adjacent to the dielectric layer. Preferably, a single photoresist layer provides an etch mask for the dielectric layer and an implant mask for the dopant.

Abstract: An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface.

Abstract: The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping.

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract: An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide.

Abstract: A method of making an IGFET includes providing a semiconductor substrate with an active region, forming a gate over the active region, forming displacement material segments over portions of the active region outside the gate, implanting a dopant into the gate, the displacement material segments and the active region using a single implant step, such that a peak concentration of the dopant is in the gate and the displacement material segments, and a light concentration of the dopant implanted through one of the displacement material segments forms a lightly doped drain region in the active region, and forming a source and a drain wherein the drain includes the lightly doped drain region. In this manner, the lightly doped drain region and heavy doping for the gate can be provided using a single implant step.

Abstract: It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. Etching in the vertical dimension is precisely controlled to resolutions of about 0.1 .mu.m while advanced photolithographic techniques in a volume production environment achieve resolutions of 0.25 .mu.m. Interconnect structures for connecting to high density vertical transistors are formed by depositing metal into the trenches etched during fabrication of the vertical transistors. A method of fabricating an integrated circuit includes etching a trench with a sidewall in a substrate wafer and forming a vertical transistor on the sidewall. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer.

Abstract: A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.

Abstract: A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.

Abstract: A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region.

Abstract: A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom surface of the trench between the spacers, forming a gate electrode on the gate insulator and the spacers, removing at least portions of the spacers to form voids in the trench after forming the gate electrode, implanting localized source and drain regions through the voids and through the bottom surface of the trench outside the gate electrode, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the dopant concentration of the localized source and drain regions is controlled by the amount of the spacers, if any, left intact when the localized source and drain regions are implanted after removing the portions of the spacers.

Abstract: A method of making enhancement-mode and depletion-mode IGFETs with different gate materials is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate composed of a first gate material over the first device region, forming a second gate composed of a second gate material over the second device region, implanting a dopant into the substrate and into the first and second gates to implant source and drain regions in the first device region and source and drain regions in the second device region, and transferring the dopant through the first gate into a first channel region in the first device region beneath the first gate without transferring essentially any of the dopant through the second gate into a second channel region in the second device region beneath the second gate, thereby providing depletion-mode doping in the first channel region while retaining enhancement-mode doping in the second channel region.

Abstract: A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the isolation structure, depositing a polysilicon blanket layer overlying the thin oxide layer, patterning a photoresist mask overlying the polysilicon blanket layer and implanting dopant impurities into the polysilicon blanket layer. The method further includes steps of diffusing the dopant impurities from the polysilicon blanket layer through the thin oxide layer into the integrated circuit device channel, removing the polysilicon blanket layer, and removing the thin oxide layer.

Abstract: It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates.

Abstract: A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

Abstract: A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask usi

Abstract: A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance.

Abstract: A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract: A method of forming an IGFET includes forming a trench with opposing sidewalls and a bottom surface in a substrate, selectively growing an oxide layer on the bottom surface so that the oxide layer includes a thick region between thin regions, implanting localized source and drain regions through the thin regions using the thick region as an implant mask, stripping the oxide layer, forming a gate insulator and gate electrode in the trench, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the locations and dopant concentrations of the localized source and drain regions are controlled by the dimensions of the selectively grown oxide layer.