Abstract: An ESD protection device and a method for forming the ESD protection device in an active region (13) which is devoid of a field oxide (14). A P type dopant region (22) and an N type dopant region (27) are formed in a semiconductor substrate (11) using photolithographic techniques, wherein they are spaced apart from each other by a spacer region (29). An anode electrode (33) contacts the P type dopant region (22) and a cathode electrode (34) contacts the N type dopant region (27). A parasitic diode resistance of the ESD protection device is governed by the width of the spacer region (29) which, in turn, is governed by the resolution of the photolithographic techniques. Thus, the present invention provides a method for lowering both the parasitic diode resistance and clamp voltage of the ESD protection device which serves to protect integrated circuits from large voltage transients.

Abstract: A mixed mode buffer circuit 11 including a first input (12), a second input (13), and an output (14). A voltage exceeding a supply voltage of mixed mode buffer circuit 11 can be applied to the output (14) without latchup or an increase in leakage current. The mixed mode buffer includes an output transistor (24) of a first conductivity type having a first electrode coupled to the output (14), a control electrode coupled to the first input (12), a second electrode coupled for receiving the supply voltage, and a bulk electrode. A first transistor (19) biases the bulk electrode when the voltage at the output is within a first predetermined range. A first bulk bias circuit (28) biases the bulk electrode when the output voltage is within a second predetermined range. A second bulk bias circuit (27) and a second transistor (18) couples the voltage at the output to the bulk electrode and the control electrode respectively, when the output voltage exceeds the second predetermined range.