Abstract: A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

Abstract: A front-end electronic circuitry for an electromagnetic radiation sensor application comprises a charge sensitive amplifier stage with a first single-input operational transconductance amplifier, and a transistor being arranged in a first feedback path of the first single-input operational transconductance amplifier, and a signal shaper stage with a second single-input operational transconductance amplifier, and an active feedback circuit being arranged in a second feedback path of the second single-input operational transconductance amplifier. The front-end electronic circuitry further comprises a control circuit having a second transistor. The control circuit is configured to provide a control signal to control the transistor of the first feedback path in dependence on a gate-source voltage of the second transistor.

Abstract: A front-end electronic circuitry for a photon counting application includes an input node to receive an input signal, an output node to provide an output signal, a charge sensitive amplifier, and a feedback element having a variable resistance. The charge sensitive amplifier includes an amplifier circuit having an input side being coupled to the input node and an output side to provide the output signal, and a capacitor being arranged in a first feedback path between the input side and the output side of the amplifier circuit. The feedback element is arranged in a second feedback path in parallel to the capacitor. The variable resistance of the feedback element is dependent on a level of the output signal.

Abstract: An electric circuitry for baseline extraction in a photon counting system includes an input signal integrity detector to determine an integrity of an input signal for baseline extraction, a sampling circuit to sample the input signal during a sampling time, and to provide a sampled version of the input signal, a signal processing circuit to process the sampled version of the input signal, and a signal processing controller to control the signal processing circuit. The input signal integrity detector is configured to determine the integrity of the input signal for baseline extraction by evaluating the input signal or the sampled version of the input signal. The signal processing controller is configured to control the signal processing circuit so that the sampled version of the input signal is processed, when the integrity of the input signal for baseline extraction is determined by the input signal integrity detector at least during the sampling time.

Abstract: A front-end electronic circuitry for a photon counting application includes a charge sensitive amplifier including an amplifier circuit and a capacitor being arranged in a feedback path between the input side and the output side of the amplifier circuit. A controllable switch is arranged in parallel to the capacitor. The circuitry includes a delay circuit to provide a delay circuit output signal being a time-delayed representation of the charge sensitive amplifier output signal. An output signal generation circuit is configured to generate the output signal by subtracting the delay circuit output signal from the charge sensitive amplifier output signal.

Abstract: A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

Abstract: A circuit arrangement is provided which includes an array of stages for photon counting current to voltage conversion. Each stage includes a tunable operational transconductance amplifier and a feedback network forming a feedback loop of the operational transconductance amplifier. Each stage is configured to provide an output signal as a function of an input signal that is provided to the amplifier input of the operational transconductance amplifier, wherein the input signal comprises one or more current pulses and the output signal comprises one or more voltage pulses. With the tunable operational transconductance amplifier the transconductance of a stage can be tuned so that differences in peaking time and gain are avoided. Furthermore, an imaging device and a method for operating a circuit arrangement are provided.

Abstract: In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Abstract: A differential switched capacitor neural amplifier comprises a sampling stage (SMP) with a plurality of differential inputs for receiving a plurality of input voltages and with at least one pair of digitally adjustable charge stores for sampling the plurality of input voltages, a summation stage (SM) for summing up charges resulting from the sampled plurality of input voltages in order to generate a summation signal, the summation stage (SM) being connected downstream to the sampling stage (SMP), and a buffer and activation stage (ACB) that is configured to apply an activation function and to generate a buffered output voltage at a differential output, based on the summation signal.

Abstract: A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

Abstract: The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

Abstract: The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

Abstract: In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Abstract: An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).

Abstract: In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal.

Abstract: An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).

Abstract: In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal.