Abstract: The present invention relates to a sigma-delta analogue-to-digital converter. The sigma-delta analogue-to-digital converter comprises a transconductance stage having first, second and third terminals. A capacitor is connected in parallel at the third terminal. Further, the sigma-delta analogue-to-digital converter comprises a quantiser at the third terminal of the transconductance stage with feedback by a voltage digital-to-analogue converter for feeding back a feedback signal to one of the terminals of the transconductance stage.

Abstract: A data transfer system having a first control unit and a second control unit, wherein the transfer path between the two control signals is formed at least partially by a two-wire cable, by which a useful signal is transferred as a difference signal between the first control unit and the second control unit, wherein the first control unit has a transceiver and the second control unit has a receiver, wherein a measurement circuit to measure a common-mode component in the useful signal is arranged before the receiver of the second control unit, wherein an error correction circuit is provided, which produces a correction signal in accordance with the measured common-mode component, wherein a compensation circuit is arranged after the receiver, wherein the compensation circuit is designed so the useful signal received by the receiver is corrected by the correction signal.

Abstract: A driver circuit device using driver equalization in power and ground terminated transmission line channels. The driver circuit device can include a weaker pull-up driver, which is needed to pre-emphasize the pull-up signal for driver equalization in power terminated transmission line channels. The driver circuit device can also include a weaker pull-down driver, which is needed to pre-emphasize the pull-down signal for driver equalization in ground terminated transmission line channels. In the transmission line channels with power terminations, a weaker pull-up Ron is implemented. In the transmission line channels with ground terminations, a weaker pull-down Ron is implemented. Drivers implemented in power and/or ground terminated transmission line channels can be used to improve device performance, such as in signal eye opening.

Abstract: A driver circuit device using driver equalization in power and ground terminated transmission line channels. The driver circuit device can include a weaker pull-up driver, which is needed to pre-emphasize the pull-up signal for driver equalization in power terminated transmission line channels. The driver circuit device can also include a weaker pull-down driver, which is needed to pre-emphasize the pull-down signal for driver equalization in ground terminated transmission line channels. In the transmission line channels with power terminations, a weaker pull-up Ron is implemented. In the transmission line channels with ground terminations, a weaker pull-down Ron is implemented. Drivers implemented in power and/or ground terminated transmission line channels can be used to improve device performance, such as in signal eye opening.

Abstract: A driver circuit device using driver equalization in power and ground terminated transmission line channels. The driver circuit device can include a weaker pull-up driver, which is needed to pre-emphasize the pull-up signal for driver equalization in power terminated transmission line channels. The driver circuit device can also include a weaker pull-down driver, which is needed to pre-emphasize the pull-down signal for driver equalization in ground terminated transmission line channels. In the transmission line channels with power terminations, a weaker pull-up Ron is implemented. In the transmission line channels with ground terminations, a weaker pull-down Ron is implemented. Drivers implemented in power and/or ground terminated transmission line channels can be used to improve device performance, such as in signal eye opening.

Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

Abstract: In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

Abstract: A MEMS piezoelectric sensor comprises a plurality of capacitors some of which may be used for sensing and others used for feedback. The capacitors may be switched to connect or disconnect selected capacitors from the sensor. Embodiments convert a two port sensor into a four port sensor without significant changes in hardware design and improve SNR and correct for offset and out-of-axis errors due to process mismatch and variations.

Abstract: An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.

Abstract: Sensing structures are provided which are designed using non-conventional designs. These sensing structures have improved sensitivity and noise floor at low frequencies.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.

Abstract: A MEMS piezoelectric sensor comprises a plurality of capacitors some of which may be used for sensing and others used for feedback. The capacitors may be switched to connect or disconnect selected capacitors from the sensor. Embodiments convert a two port sensor into a four port sensor without significant changes in hardware design and improve SNR and correct for offset and out-of-axis errors due to process mismatch and variations.

Abstract: An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.

Abstract: According to some embodiments, a sigma-delta analog-to-digital converter includes a junction, to receive the analog signal along with a feedback signal, and a loop filter coupled to the junction. An n-bit analog-to-digital converter, coupled to the loop filter, may provide the digital output of the sigma-delta analog-to-digital converter. In addition, an n-bit feedback digital-to-analog converter, with a plurality of cells, may receive the digital output and generate the feedback signal, wherein the feedback converter is associated with at least one calibration digital-to-analog converter.

Abstract: Sensing structures are provided which are designed using non-conventional designs. These sensing structures have improved sensitivity and noise floor at low frequencies.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number. By using a DLL to take a timing measurement, the effect of process and temperature variations is reduced by the closed loop feedback of the DLL. In another embodiment, a multiplying DLL (MDLL) is used.

Abstract: The present invention relates to a controlled current source having a control input, in particular for digital/analogue converters in continuous-time sigma/delta modulators, having a current source (4) with a control input which generates an output current dependent on a control voltage applied to the control input, and having a controller (7) for converting a clock signal into a voltage signal, with the controller (7) being connected to the current source (4) in such a manner that the voltage signal is applied as a control voltage to the control input of the current source (4). The controller is designed to is designed to convert the clock signal into a voltage signal which has within a clock duration a reproducible curve ending with a falling flank. Using the present controlled current source in a digital/analogue converter in a feedback branch of a continuous-time sigma/delta modulator permits realizing a sigma/delta modulator which is essentially insensitive to clock jitter.

Abstract: The present invention relates to a controlled current source having a control input, in particular for digital/analogue converters in continuous-time sigma/delta modulators, having a current source (4) with a control input which generates an output current dependent on a control voltage applied to the control input, and having a controller (7) for converting a clock signal into a voltage signal, with the controller (7) being connected to the current source (4) in such a manner that the voltage signal is applied as a control voltage to the control input of the current source (4). The controller is designed to is designed to convert the clock signal into a voltage signal which has within a clock duration a reproducible curve ending with a falling flank. Using the present controlled current source in a digital/analogue converter in a feedback branch of a continuous-time sigma/delta modulator permits realizing a sigma/delta modulator which is essentially insensitive to clock jitter.