Abstract: A cross table for a woodworking machine, such as a sliding table saw, and to a woodworking machine having such a cross table. The cross table includes a horizontally lying first workpiece support surface, a stop rail arranged above the first workpiece support surface and having a first workpiece stop surface on a first side of the stop rail, which is arranged such that a workpiece resting on the first workpiece support surface horizontally in front of the stop rail can be placed with a side edge against the workpiece stop surface. The stop rail has a second workpiece stop surface on a second side of the stop rail opposite the first side, the second workpiece stop surface arranged such that a workpiece resting on the first workpiece support surface horizontally behind the stop rail can be placed with a side edge against the workpiece stop surface.

Abstract: A safety device for machine tools, such as a panel-sizing circular saw or an edge-gluing machine, with a machining tool used for machining a workpiece supplied to the machine tool, comprises a detection device and a hazard reduction device. The detection device is designed to detect a hazardous situation of an operator of the machine tool and the hazard reduction device is designed to initiate a safety measure to reduce the risk of injury to the operator when a hazard signal characterizing a hazardous situation of the operator is received.

Abstract: A safety device for machine tools, such as a panel-sizing circular saw or an edge-gluing machine, with a machining tool used for machining a workpiece supplied to the machine tool, comprises a detection device and a hazard reduction device. The detection device is designed to detect a hazardous situation of an operator of the machine tool and the hazard reduction device is designed to initiate a safety measure to reduce the risk of injury to the operator when a hazard signal characterizing a hazardous situation of the operator is received.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

Abstract: A semiconductor circuit is provided having a crossbar switch arrangement, which includes at least one multiplexer, an output of which corresponds to an output of the crossbar switch arrangement. The arrangement also includes: a set of input lines connected to data inputs of the multiplexer, the input lines extending along a first direction of the semiconductor circuit; and a set of select lines connected to select inputs of the multiplexer, the select lines extending along a second direction of the semiconductor circuit, where the second direction differs from the first direction. The multiplexer includes at least one multiplexing circuit for generating a multiplexed signal from signals present at the input lines and at least one primary output driver for generating an output signal from the multiplexed signal.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.

Abstract: An end point report is created from a comprehensive timing report following steps that include: receiving a comprehensive timing report for an electronic circuit, determining a timing data set for a start pin, determining a worst timing path that includes the start pin based, at least in part, upon the comprehensive timing report, and generating an end point report for the worst timing path.