Abstract: Systems and methods for operating a filter for echo cancellation are described. In one embodiment, a method for operating a filter for echo cancellation involves monitoring at least one of a filter coefficient of the filter and an echo cancellation error to generate a monitoring result and, in response to the monitoring result, adjusting at least one of delay elements and filter taps of the filter to vary an impulse response of the filter. Other embodiments are also described.

Abstract: Systems and methods for operating a filter for echo cancellation are described. In one embodiment, a method for operating a filter for echo cancellation involves monitoring at least one of a filter coefficient of the filter and an echo cancellation error to generate a monitoring result and, in response to the monitoring result, adjusting at least one of delay elements and filter taps of the filter to vary an impulse response of the filter. Other embodiments are also described.

Abstract: A method and apparatus (200) for embedding a watermark in an information signal bit-stream are described. The method comprises receiving a portion of an information signal bit-stream (MPEG2). A first copy of the received portion is stored in a first buffer (220). A second copy of the received portion is watermarked, and the resulting watermarked signal stored in a second buffer (240). At predetermined intervals, a check is performed to determine if the bit-rate of the received portion has been changed by being watermarked. If the check determines the bit-rate has changed, the first copy of the received portion from the first buffer is output. Otherwise the watermarked signal from the second buffer is output.

Abstract: A signal processing technique for generating and processing trick play information for recording on a record carrier is used in an apparatus for recording a digital information signal onto a record carrier, in which the apparatus includes a first error correction encoder for error correcting trick play sync blocks generated from the digital information signal, a second error correction encoder for error correcting sync blocks formed from sync blocks of the digital information signal and the error corrected trick play sync blocks, and a third error correction encoder for error correcting each of the error corrected sync blocks. In the technique, the order that the trick play sync blocks provided by the first error correction encoder to the second error correction encoder is not the same as the order in which the third error correction encoder supplies the trick play sync blocks to the writing heads.

Abstract: In order to find the position of the boundary between transmitted codewords, in a receiver a reliability measure for two possible positions are compared. If a relative difference measure of these reliability measure exceeds a predetermined threshold value, the reliability measure indicating the largest reliability corresponds to the correct position of the boundary between the codewords.

Abstract: In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.

Abstract: In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to avoid this undesired injection of charge, the input is provided with means by which it is ensured that the storage site under the input gate is entirely empty during the SP transport.

Abstract: An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different procedures for generating the de-interlacing clocks for the odd channels and for the even channels of the parallel section. These procedures are carried out sequentially with an adjustable difference in time.

Abstract: The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

Abstract: In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.

Abstract: A field number doubling circuit has a measuring circuit (25) for determining the starting instant of a second read operation of a memory circuit (3) with respect to that of a first read operation in such a way that a display of a field number doubled television signal, even for a non-standard television signal to be doubled in field number, does not exhibit any flicker at the field frequency of the last-mentioned signal. Furthermore, the measuring circuit can determine the most favorable waiting period (B) between a write operation and a first read operation, the waiting period (A) between a vertical synchronizing pulse (V) and the start of a memory write operation, and a value for the waiting period (C) between the start of a memory read operation and the start of vertical deflection of a picture display section (13). A counter circuit (29) which can be controlled by means of the measuring circuit is provided for the controllable periods.

Abstract: In a television signal memory write circuit which is synchronized by horizontal and vertical synchronizing signal patterns obtained from the television signal to be entered, the mutual positions of these patterns being measured with the aid of a measuring circuit; and depending on this measurement, the vertical synchronizing signal pattern is delayed by a variable delay circuit such that in practice the patterns are prevented from coinciding, thereby preventing a change in the position of a predetermined line number in the television signal memory circuit. This renders the circuit less sensitive to interference.

Abstract: A data processing system comprising a memory receives data in the form of data blocks. Such a data block contains at least one data word and check bits. On the basis of the check bits it is vertified whether the data block contains reliable or unreliable data words. The unreliable data words are not written into the memory but are replaced by an unreliability indicator which is written into the memory at the address reserved for the unreliable dataword in question.