Patents by Inventor Fritz Kirscht

Fritz Kirscht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8968467
    Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides semiconductor predominantly of a single type (p-type or n-type) for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of boron, phosphorus, aluminum and/or gallium. The process further melts the silicon feedstock with the boron, phosphorus, aluminum and/or gallium to form a molten silicon solution from which to perform directional solidification and maintains the homogeneity of the resistivity of the silicon throughout the ingot. A balanced amount of phosphorus can be optionally added to the aluminum and/or gallium. Resistivity may also be measured repeatedly during ingot formation, and additional dopant may be added in response, either repeatedly or continuously.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 3, 2015
    Assignee: Silicor Materials Inc.
    Inventors: Fritz Kirscht, Marcin Walerysiak, Matthias Heuer, Anis Jouini, Kamel Ounadjela
  • Patent number: 8882912
    Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 11, 2014
    Assignee: Silicor Materials Inc.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Patent number: 8547121
    Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: October 1, 2013
    Assignee: Silicor Materials Inc.
    Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
  • Publication number: 20130171052
    Abstract: The invention describes a process for removing nonmetallic impurities from metallurgical silicon. A melt is produced from metallurgical silicon and halide-containing silicon. As a result, the impurities are sublimed out and removed from the melt in the form of nonmetal halides. Compared with the known process, in which gaseous halogen is blown through an Si melt, the novel process can be carried out in a particularly simple and efficient manner.
    Type: Application
    Filed: July 29, 2009
    Publication date: July 4, 2013
    Inventors: Seyed-Javad Mohsseni-Ala, Christian Bauch, Rumen Deltschew, Thoralf Gebel, Gerd Lippold, Matthias Heuer, Fritz Kirscht, Kamel Ounadjela
  • Publication number: 20110309478
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Applicant: Calisolar, Inc.
    Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
  • Publication number: 20110210470
    Abstract: The present invention relates to efficient furnace capacity utilization in the production of ingots. The present invention includes a crucible and use of the same. The crucible approximately matches the interior shape of the furnace in which the ingots are produced.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 1, 2011
    Applicant: 6N Silicon Inc.
    Inventors: Scott Nichol, Dan Smith, Damon Dastgiri, Fritz Kirscht
  • Publication number: 20110211995
    Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Applicant: Calisolar, Inc.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Patent number: 8008107
    Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: August 30, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
  • Patent number: 7955433
    Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: June 7, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Patent number: 7887633
    Abstract: Techniques for the formation of silicon ingots and crystals using silicon feedstock of various grades are described. Common feature is adding a predetermined amount of germanium to the melt and performing a crystallization to incorporate germanium into the silicon lattice of respective crystalline silicon materials. Such incorporated germanium results in improvements of respective silicon material characteristics, mainly increased material strength. This leads to positive effects at applying such materials in solar cell manufacturing and at making modules from those solar cells. A silicon material with a germanium concentration in the range (50-200) ppmw demonstrates an increased material strength, where best practical ranges depend on the material quality generated.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: February 15, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Anis Jouini, Dieter Linke, Martin Kaes, Jean Patrice Rakotoniaina, Kamel Ounadjela
  • Publication number: 20100327890
    Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.
    Type: Application
    Filed: April 29, 2010
    Publication date: December 30, 2010
    Applicant: CaliSolar, Inc.
    Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
  • Publication number: 20100310445
    Abstract: A process control method for UMG-Si purification by performing a directional solidification of molten UMG-Si to form a silicon ingot is described. The ingot is divided into bricks and the resistivity profile of each silicon brick is mapped. A crop line for removing the impurities concentrated and captured in the ingot during the directional solidification is calculated based on the resistivity map. The concentrated impurities are then removed by cropping each brick along that brick's calculated crop line.
    Type: Application
    Filed: February 10, 2010
    Publication date: December 9, 2010
    Applicant: CaliSolar, Inc.
    Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
  • Publication number: 20100258768
    Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides semiconductor predominantly of a single type (p-type or n-type) for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of boron, phosphorus, aluminum and/or gallium. The process further melts the silicon feedstock with the boron, phosphorus, aluminum and/or gallium to form a molten silicon solution from which to perform directional solidification and maintains the homogeneity of the resistivity of the silicon throughout the ingot. A balanced amount of phosphorus can be optionally added to the aluminum and/or gallium. Resistivity may also be measured repeatedly during ingot formation, and additional dopant may be added in response, either repeatedly or continuously.
    Type: Application
    Filed: November 13, 2009
    Publication date: October 14, 2010
    Applicant: CALISOLAR, INC.
    Inventors: Fritz Kirscht, Marcin Walerysiak, Matthias Heuer, Anis Jouini, Kamel Ounadjela
  • Patent number: 7651566
    Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides a predominantly p-type semiconductor for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of aluminum or/and gallium. The process further melts the silicon feedstock together with a predetermined amount of aluminum or/and gallium to form a molten silicon solution from which to perform directional solidification and, by virtue of adding aluminum or/and gallium, maintains the homogeneity the resistivity of the silicon ingot throughout the silicon ingot. In the case of feedstock silicon leading to low resistivity in respective ingots, typically below 0.4 ?cm, a balanced amount of phosphorus can be optionally added to aluminum or/and gallium.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 26, 2010
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Publication number: 20090308455
    Abstract: Techniques for the formation of silicon ingots and crystals using silicon feedstock of various grades are described. Common feature is adding a predetermined amount of germanium to the melt and performing a crystallization to incorporate germanium into the silicon lattice of respective crystalline silicon materials. Such incorporated germanium results in improvements of respective silicon material characteristics, mainly increased material strength. This leads to positive effects at applying such materials in solar cell manufacturing and at making modules from those solar cells. A silicon material with a germanium concentration in the range (50-200) ppmw demonstrates an increased material strength, where best practical ranges depend on the material quality generated.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Applicant: CALISOLAR, INC.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Anis Jouini, Dieter Linke, Martin Kaes, Jean Patrice Rakotoniaina, Kamel Ounadjela
  • Publication number: 20090223549
    Abstract: Formation of a solar cell device from upgraded metallurgical grade silicon which has received at least one defect engineering process and including a low contact resistance electrical path. An anti-reflective coating is formed on an emitter layer and back contacts are formed on a back surface of the bulk silicon substrate. This photovoltaic device may be fired to form a back surface field at a temperature sufficiently low to avoid reversal of previous defect engineering processes. The process further forms openings in the anti-reflective coating and a low contact resistance metal layer, such as nickel layer, over the openings in the anti-reflective coating. The process may anneal the low contact resistance metal layer to form n-doped portion and complete an electrically conduct path to the n-doped layer. This low temperature metallization (e.g., <700° C.) supports the use of UMG silicon for the solar device formation without the risk of reversing earlier defect engineering processes.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 10, 2009
    Applicant: CaliSolar, Inc.
    Inventors: Kamel Ounadjela, Jean Patrice Rakotoniaina, Martin Kaes, Dirk Zickermann, Alain Blosse, Abdellatif Zerga, Matthias Heuer, Fritz Kirscht
  • Patent number: 7521954
    Abstract: A method of determining a diffusion length of a minority carrier in a material which includes applying a first excitation light having a first photon flux to a material, measuring a first surface photo voltage resulting from the application of the first excitation light, applying a second excitation light having a second photon flux to the material, measuring a second surface photo voltage resulting from the application of the second excitation light, applying a third excitation light having a third photon flux, having a predetermined ratio to the first photon flux, to the material, measuring a third surface photo voltage resulting from the application of the third excitation light, determining a diffusion length of a minority carrier in the material based on the measured first, second and third surface photo voltages.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: April 21, 2009
    Assignee: Sumco Corporation
    Inventors: Benno Orschel, Andrzej Buczkowski, Fritz Kirscht
  • Publication number: 20090026423
    Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides a predominantly p-type semiconductor for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of aluminum or/and gallium. The process further melts the silicon feedstock together with a predetermined amount of aluminum or/and gallium to form a molten silicon solution from which to perform directional solidification and, by virtue of adding aluminum or/and gallium, maintains the homogeneity the resistivity of the silicon ingot throughout the silicon ingot. In the case of feedstock silicon leading to low resistivity in respective ingots, typically below 0.4? cm, a balanced amount of phosphorus can be optionally added to aluminum or/and gallium.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 29, 2009
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Publication number: 20090028773
    Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.
    Type: Application
    Filed: July 26, 2007
    Publication date: January 29, 2009
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Publication number: 20080257254
    Abstract: Techniques for the formation of a large grain, multi-crystalline semiconductor ingot and include forming a silicon melt in a crucible, the crucible capable of locally controlling thermal gradients within the silicon melt. The local control of thermal gradients preferentially forms silicon crystals in predetermined regions within the silicon melt by locally reducing temperatures is the predetermined regions. The method and system control the rate at which the silicon crystals form using local control of thermal gradients for inducing the silicon crystals to obtain preferentially maximal sizes and, thereby, reducing the number of grains for a given volume. The process continues the thermal gradient control and the rate control step to form a multicrystalline silicon ingot having reduced numbers of grains for a given volume of the silicon ingot.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Inventors: Dieter Linke, Matthias Heuer, Fritz Kirscht, Jean Patrice Rakotoniana, Kamel Ounadjela