Patents by Inventor FU-CHING HSU
FU-CHING HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230205623Abstract: A method for scanning bad block of a memory and a circuit system thereof are provided. In a procedure of scanning bad blocks of the memory, the circuit system uses a cache read command that is adapted to a process of continuously reading a plurality of memory pages of the memory. The cache read command loads a memory page data to a cache of the memory in advance, and then reads the memory page data from the cache at a next instruction cycle. Next, the cache read command loads a next memory page data to the cache. These steps are repeated until the procedure of scanning bad blocks of the memory is completed. The method can effectively reduce the time for the memory to prepare the next page data so as to reduce the impact of the busy time of the memory on time performance.Type: ApplicationFiled: December 23, 2022Publication date: June 29, 2023Inventor: FU-CHING HSU
-
Patent number: 11501845Abstract: A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.Type: GrantFiled: June 4, 2021Date of Patent: November 15, 2022Assignee: Realtek Semiconductor Corp.Inventors: Chia-Jung Chang, Chiu-Yun Tsai, Fu-Ching Hsu
-
Publication number: 20210383889Abstract: A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.Type: ApplicationFiled: June 4, 2021Publication date: December 9, 2021Inventors: Chia-Jung Chang, Chiu-Yun Tsai, Fu-Ching Hsu
-
Patent number: 11122305Abstract: A multimedia streaming and network apparatus that includes a flash memory, a network module, an access module and a multimedia streaming module is provided. The network module includes a network processing circuit. The access module includes a flash memory controller and an access circuit. The flash memory controller controls and accesses the flash memory. The access circuit includes a network processing storage circuit, a command and data transmission circuit and an interface converting circuit. The command and data transmission circuit performs transmission of command and data between the processing storage circuit and the network processing circuit. The interface converting circuit performs transmission and interface conversion between the network processing storage circuit and the flash memory controller. The multimedia streaming module accesses the flash memory through the flash memory controller.Type: GrantFiled: July 30, 2019Date of Patent: September 14, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chia-Jung Chang, Chien-Lien Peng, Fu-Ching Hsu
-
Patent number: 11093434Abstract: A communication system includes a physical layer circuit, a link layer circuit, a transport layer circuit, and a memory circuit. The physical layer circuit is coupled to a first storage circuit. The link layer circuit is coupled to the physical layer circuit. The transport layer circuit is coupled to a second storage circuit. The memory circuit is coupled between the link layer circuit and the transport layer circuit. The memory circuit includes a memory. The memory is controlled to selectively transmit data in the second storage circuit to the first storage circuit, or transmit data in the first storage circuit to the second storage circuit.Type: GrantFiled: May 6, 2020Date of Patent: August 17, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Fu-Ching Hsu
-
Patent number: 11055255Abstract: An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.Type: GrantFiled: January 14, 2020Date of Patent: July 6, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Fu-Ching Hsu, Chih-Wei Chang
-
Publication number: 20210124709Abstract: A communication system includes a physical layer circuit, a link layer circuit, a transport layer circuit, and a memory circuit. The physical layer circuit is coupled to a first storage circuit. The link layer circuit is coupled to the physical layer circuit. The transport layer circuit is coupled to a second storage circuit. The memory circuit is coupled between the link layer circuit and the transport layer circuit. The memory circuit includes a memory. The memory is controlled to selectively transmit data in the second storage circuit to the first storage circuit, or transmit data in the first storage circuit to the second storage circuit.Type: ApplicationFiled: May 6, 2020Publication date: April 29, 2021Inventor: Fu-Ching HSU
-
Publication number: 20200341936Abstract: An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.Type: ApplicationFiled: January 14, 2020Publication date: October 29, 2020Inventors: Fu-Ching HSU, Chih-Wei CHANG
-
Patent number: 10776051Abstract: A memory sharing dual-mode network communication device includes a first memory, an OTT module and a PON module. The first memory is divided into an OTT region and a PON region, and the OTT module is used to obtain an OTT service, which includes an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit, and a memory slave controller. The PON module includes a PON processor and a second memory main controller. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request of the PON processor to access the OTT area or the PON area of the first memory through the first memory host controller, and the memory arbitration circuit further determines the priority order of the first access request and the second access request.Type: GrantFiled: May 14, 2019Date of Patent: September 15, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ming-Tsung Tsai, Chiu-Yun Tsai, Chien-Lien Peng, Fu-Ching Hsu
-
Publication number: 20200275137Abstract: A multimedia streaming and network apparatus that includes a flash memory, a network module, an access module and a multimedia streaming module is provided. The network module includes a network processing circuit. The access module includes a flash memory controller and an access circuit. The flash memory controller controls and accesses the flash memory. The access circuit includes a network processing storage circuit, a command and data transmission circuit and an interface converting circuit. The command and data transmission circuit performs transmission of command and data between the processing storage circuit and the network processing circuit. The interface converting circuit performs transmission and interface conversion between the network processing storage circuit and the flash memory controller. The multimedia streaming module accesses the flash memory through the flash memory controller.Type: ApplicationFiled: July 30, 2019Publication date: August 27, 2020Inventors: Chia-Jung CHANG, Chien-Lien PENG, Fu-Ching HSU
-
Publication number: 20200210109Abstract: A memory sharing dual-mode network communication device includes a first memory, an OTT module and a PON module. The first memory is divided into an OTT region and a PON region, and the OTT module is used to obtain an OTT service, which includes an OTT processor, a memory arbitration circuit, a first memory main controller, a bridge circuit, and a memory slave controller. The PON module includes a PON processor and a second memory main controller. The memory arbitration circuit is configured to respond to a first access request from the OTT processor or a second access request of the PON processor to access the OTT area or the PON area of the first memory through the first memory host controller, and the memory arbitration circuit further determines the priority order of the first access request and the second access request.Type: ApplicationFiled: May 14, 2019Publication date: July 2, 2020Inventors: MING-TSUNG TSAI, CHIU-YUN TSAI, CHIEN-LIEN PENG, FU-CHING HSU