Abstract: A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.

Abstract: A method for error handling of an interconnection protocol, a controller, and a storage device are provided. The method includes receiving a frame error position indication signal to indicate whether an error occurs in a frame in each clock cycle and a symbol position corresponding to the error, and receiving a frame correction position indication signal to indicate whether the frame in each clock cycle is correct and a symbol position corresponding to the frame that is correct; according to the frame error position indication signal and the frame correction position indication signal, determining that a frame error occurs in a first clock cycle, and after requesting for NAC frame transmission, sending a request for disabling the NAC frame transmission; and after the first clock cycle, comparing the frame error position indication signal and the frame correction position indication signal.

Abstract: A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.

Abstract: A method for data processing of frame receiving of an interconnection protocol and a storage device, for use in a first device linkable to a second device according to the interconnection protocol. The method includes: in processing of frames originating from the second device and received by the first device: while sending data contained in a first frame to a network layer from a data link layer, pre-fetching symbols of a second frame; and after the data contained in the first frame are sent to the network layer and the symbols of the second frame are pre-fetched, sending data contained in the second frame to the network layer. Upon receipt of back-to-back frames, the efficiency of the frame receiving at the data link layer is enhanced.

Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

Abstract: A method for error handling of an interconnection protocol, a controller, and a storage device are provided. The method includes receiving a frame error position indication signal to indicate whether an error occurs in a frame in each clock cycle and a symbol position corresponding to the error, and receiving a frame correction position indication signal to indicate whether the frame in each clock cycle is correct and a symbol position corresponding to the frame that is correct; according to the frame error position indication signal and the frame correction position indication signal, determining that a frame error occurs in a first clock cycle, and after requesting for NAC frame transmission, sending a request for disabling the NAC frame transmission; and after the first clock cycle, comparing the frame error position indication signal and the frame correction position indication signal.

Abstract: A method for data processing of frame receiving of an interconnection protocol and a storage device, for use in a first device linkable to a second device according to the interconnection protocol. The method includes: in processing of frames originating from the second device and received by the first device: while sending data contained in a first frame to a network layer from a data link layer, pre-fetching symbols of a second frame; and after the data contained in the first frame are sent to the network layer and the symbols of the second frame are pre-fetched, sending data contained in the second frame to the network layer. Upon receipt of back-to-back frames, the efficiency of the frame receiving at the data link layer is enhanced.

Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

Abstract: A shock-resistant magnetic storage medium includes a circuit protection module coupled between a power converter and a magnetic disk assembly. The circuit protection module includes an acceleration sensor for generating output signals that indicate a falling state of the magnetic disk assembly, a switch operable so as to make or break a circuit connection between the power converter and the magnetic disk assembly, and a processor for controlling the switch to break the circuit connection between the power converter and the magnetic disk assembly based on the output signals from the acceleration sensor so as to interrupt supply of electric power to the magnetic disk assembly when the magnetic disk assembly is dropped.

Abstract: A continuous heat sink adapted to an electronic device comprises a prefabricated slat folded into a plurality of perforated sections to define segregated spaces for ventilation and adhered by glue or fasteners to a base plate with a skirt folded at a right angle to each section; the base plate then is placed on the top of the electronic device for the heat to be conducted to the heat sink for dissipation, further improved by the holes that promote the lateral airflow.

Abstract: An elastic clamp structure of an interface socket is provided, which consists of an interface socket with two clamps. The clamp has a pressed flat block at each free end, in which the flat block extends out from one side of the cylindrical surface of the wire, while the other side of the flat block maintains the cylindrical surface contour of the wire. The height of the flat block is larger than the inside height of the projecting lug, and smaller than the width of the projecting lug of the interface socket, allowing the clamp to swivel smoothly.