Abstract: The disclosure relates to a face recognition system. The face recognition system includes a camera module configured to acquire face recognition information of a target object; a feature point recognition module configured to select facial feature points; a displacement output module configured to output a displacement and azimuth of the camera module during acquiring the face recognition information at different positions; a distance calculation module configured to calculate depth distances between the facial feature points and the displacement between the different positions; and a face recognition module configured to judge whether the target object is the target user. A face recognition method is also related.

Abstract: An automatic guiding system for analyzing pavement curvature in or on an autonomous mobile device comprises an image acquisition module, a pavement curvature analysis module, a posture sensing module, and a pavement curvature database. The image acquisition module collects pavement curvature images as the autonomous mobile device moves. The pavement curvature analysis module processes the pavement curvature images, and extracts contour information of the pavement curvature images. The posture sensing module continuously senses the posture of the autonomous mobile device. The pavement curvature database is configured to stores the contour information and the posture.

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.

Abstract: An antenna for use in an electronic device includes an antenna body and two elastic conductors, the antenna body is attached to the inside wall of the electronic device, includes a feeding-in portion and a grounding portion, the feeding-in portion is connected to a printed circuit board through a elastic conductor for feeding-in, and the grounding is connected to the printed circuit board for grounding.

Abstract: An antenna structure includes a first antenna and a second antenna both connected to a PCB of an electronic device and a grounded metal sheet arranged between the first antenna and the second antenna. The metal sheet forms a capacitor and an inductor, and the capacitor and the inductor form a filtering circuit that is able to reduce interference between the first antenna and the second antenna.

Abstract: A printed circuit board includes an antenna, an EMI source, and inductor. The EMI source is connected to the printed circuit board by a pin. The inductor is connected between the pin and a ground of the printed circuit board. The connected inductor increases the resonant frequency of the EMI source to make the resonant frequency of EMI source away from the antenna. Thereby the EMI generated by the EMI source is decreased and the radiation efficiency of the antenna increases.

Abstract: An electronic device includes a first antenna and a second antenna both defined in a housing of the electronic device and respectively connected to a PCB of the electronic device by a component. A slot is defined between the first antenna and the second antenna. The slot forms a capacitor and an inductor to form a filtering circuit for reducing interference between the first antenna and the second antenna.

Abstract: A hinge assembly includes an axle portion having first and second ends, a first hinged portion, a second hinged portion, and at least one conductive member. The first hinged portion is inserted into one end of the axle portion. The other end of the axle portion is received the second hinged portion. The conductive member is positioned between the axle portion and one of the first hinged portion and the second hinged portion.

Abstract: A hinge assembly includes an axle portion having first and second ends, a first hinged portion, a second hinged portion, and at least one conductive member. The first hinged portion is inserted into one end of the axle portion. The other end of the axle portion is received the second hinged portion. The conductive member is positioned between the axle portion and one of the first hinged portion and the second hinged portion.

Abstract: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.