Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.

Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Abstract: An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: activate an eye-diagram analyzer to adjust a parameter of an equalizer according to magnitudes corresponding to an eye-diagram, which are generated by the eye-diagram analyzer, and repeatedly adjust a parameter of the equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state. The symbol decoding error is detected during a reception of host data from a host side according to a command issued by the host side, which is defined in Universal Flash Storage (UFS) specification.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: activate an eye-diagram analyzer to adjust a parameter of an equalizer according to magnitudes corresponding to an eye-diagram, which are generated by the eye-diagram analyzer, and repeatedly adjust a parameter of the equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state. The symbol decoding error is detected during a reception of host data from a host side according to a command issued by the host side, which is defined in Universal Flash Storage (UFS) specification.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: repeatedly adjust a parameter of an equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a de-emphasis adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a thermal sensor. The thermal sensor senses ambient temperature to obtain a sensed temperature and provides the sensed temperature to the processor. When the processor determines that the sensed temperature is higher than a high-temperature threshold, the processor adjusts a data transfer speed of the predetermined interface according to a data processing speed required by subsequent data to be read from or written to the data storage device.

Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

Abstract: A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.

Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.