Patents by Inventor Fu-Jye Liang
Fu-Jye Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11594528Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.Type: GrantFiled: May 26, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 11150561Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.Type: GrantFiled: July 13, 2020Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Publication number: 20210296303Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.Type: ApplicationFiled: May 26, 2021Publication date: September 23, 2021Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Patent number: 11024623Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.Type: GrantFiled: July 20, 2020Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 10871713Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.Type: GrantFiled: May 4, 2020Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Publication number: 20200348586Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.Type: ApplicationFiled: July 13, 2020Publication date: November 5, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Publication number: 20200350306Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Publication number: 20200264515Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Patent number: 10720419Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.Type: GrantFiled: July 26, 2019Date of Patent: July 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 10712651Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.Type: GrantFiled: February 27, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 10642158Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.Type: GrantFiled: October 3, 2018Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Publication number: 20190348409Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Patent number: 10366973Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.Type: GrantFiled: October 30, 2017Date of Patent: July 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Publication number: 20190163046Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.Type: ApplicationFiled: October 3, 2018Publication date: May 30, 2019Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Publication number: 20190137866Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.Type: ApplicationFiled: February 27, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Publication number: 20190131290Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
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Patent number: 10146141Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.Type: GrantFiled: August 28, 2014Date of Patent: December 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Cheng Hung, Wei-Liang Lin, Yung-Sung Yen, Chun-Kuang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Tzung-Chi Fu, Ming-Sen Tung, Fu-Jye Liang, Li-Jui Chen, Meng-Wei Chen, Kuei-Shun Chen
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Patent number: 9360767Abstract: A method includes directing a beam of radiation along an optical axis toward a workpiece support, measuring a spectrum of the beam at a first time to obtain a first profile, measuring the spectrum of the beam at a second time to obtain a second profile, determining a spectral difference between the two profiles, and adjusting a position of the workpiece support along the optical axis based on the difference. A different aspect involves an apparatus having a workpiece support, beam directing structure that directs a beam of radiation along an optical axis toward the workpiece support, spectrum measuring structure that measures a spectrum of the beam at first and second times to obtain respective first and second profiles, processing structure that determines a difference between the two profiles, and support adjusting structure that adjusts a position of the workpiece support along the optical axis based on the difference.Type: GrantFiled: April 9, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Tsun Hsieh, Chih-Ming Ke, Fu-Jye Liang, Li-Jui Chen, Tzung-Chi Fu
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Patent number: 9360778Abstract: Disclosed is a lithography system. The lithography system includes a lithography exposure tool designed for performing an exposure process to a radiation-sensitive material layer coated on an integrated circuit substrate; an alignment module coupled with the lithography exposure tool, designed for alignment measurement, and configured for transferring the integrated circuit substrate to the lithography exposure tool; and an alignment calibration module designed to calibrate the alignment module relative to the lithography exposure.Type: GrantFiled: March 2, 2012Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Jui Chen, Fu-Jye Liang, Hsueh-Hung Wu
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Publication number: 20160062250Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Inventors: Chi-Cheng Hung, Wei-Liang Lin, Yung-Sung Yen, Chun-Kuang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Tzung-Chi Fu, Ming-Sen Tung, Fu-Jye Liang, Li-Jui Chen, Meng-Wei Chen, Kuei-Shun Chen