Abstract: A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.

Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).

Abstract: A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).

Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.