Patents by Inventor Fu-To Wang

Fu-To Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240189243
    Abstract: A lipid compound or a derivative thereof and a pharmaceutical composition employing the same are provided. The lipid compound has a structure represented by Formula (I): wherein Z1, Z2, Z3 and Z4 are as disclosed in the specification.
    Type: Application
    Filed: November 13, 2023
    Publication date: June 13, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Felice Cheng, Ping-Fu Cheng, Jenn-Tsang Hwang, Chih-Wei Fu, Ku-Feng Lin, Ya-Ling Chiu, Jheng-Sian Li, Kang-Li Wang, Siou-Han Chang, Chia-Yu Fan
  • Patent number: 12006738
    Abstract: An extension device, including a connecting base and an anti-theft lock assembly, is provided. The connecting base includes a housing, a first moving member, a fixed member, and a second moving member. The fixed member is disposed at one side of the housing and includes a lock hole. The second moving member is movably disposed between the first moving member and the fixed member. The anti-theft lock assembly is detachably disposed at one side of the fixed member opposite to the second moving member. The anti-theft lock assembly is adapted to pass through the lock hole of the fixed member and push against the second moving member, so that the second moving member abuts against the first moving member to stop the first moving member at a buckling position. In addition, an electronic system, including the extension device, is also provided.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: June 11, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chun-Fu Chang, I-Tien Hsieh, Hui-Chen Wang
  • Publication number: 20240186117
    Abstract: An atomic layer deposition apparatus including a chamber, a platform, a shower head, a bias power supply, a first injection device, and a second injection device is provided. The platform and the shower head are disposed in the chamber, and the platform is configured to carry a substrate having a high aspect ratio structure. The bias power supply is coupled to the platform. The first injection device and the second injection device are connected to the chamber; the first injection device injects a first precursor or a first inert gas into the chamber along a first direction through the shower head, and the second injection device injects a second precursor or a second inert gas into the chamber along a second direction perpendicular to the first direction. When the first precursor or the second precursor is injected into the chamber, the bias power supply is turned on. When the first inert gas or the second inert gas is injected into the chamber, the bias power supply is turned off.
    Type: Application
    Filed: January 11, 2024
    Publication date: June 6, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hsuan-Fu Wang, Fu-Ching Tung, Ching-Chiun Wang
  • Publication number: 20240188306
    Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 6, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang, Hsiang-Hung Peng
  • Publication number: 20240183351
    Abstract: A U-shaped e-cigarette peristaltic pump includes: a carrier; a drive assembly; a transmission assembly; and a peristaltic assembly. The drive assembly is arranged on the carrier. The peristaltic assembly and the drive assembly are arranged side by side on a same side of the carrier. A first accommodating space is provided between the drive assembly and the carrier. A second accommodating space is provided between the peristaltic assembly and the carrier. The transmission assembly is respectively in the first accommodating space and the second accommodating space. The drive assembly is connected to the peristaltic assembly through the transmission assembly.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 6, 2024
    Inventors: Cong WU, Dongyang LI, Xiaowen WANG, Fu KE
  • Publication number: 20240185913
    Abstract: A memory device and a semiconductor die are provided. The memory device includes: a non-volatile storage device, with a first terminal coupled to a bit line; and an access transistor, configured to control electrical connection between a second terminal of the non-volatile storage device and a source line, and comprising an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) stacked on the NFET. A common source/drain terminal of the NFET and the PFET is coupled to the second terminal of the non-volatile storage device. Another common source/drain terminal of the NFET and the PFET is coupled to the source line. Further, gate terminals of the NFET and the PFET are coupled to different word lines.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Iuliana Radu
  • Publication number: 20240173395
    Abstract: Provided in the present disclosure are a Zika/dengue vaccine and its application thereof. The present disclosure introduces a mutation into the E-protein FL fusion region of the Zika virus or dengue virus. Antigens with said mutations are unable to bind to antibodies that causes ADE. After immunization with the vaccine of the present disclosure acquired from the said antigens, production of FL epitope-induced antibodies can be prevented, thereby reducing or eliminating the ADE effect.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 30, 2024
    Applicant: Institute of Microbiology, Chinese Academy of Sciences
    Inventors: Fu GAO, Lianpan DAI, Jinghua YAN, Kun XU, Yuxuan HAN, Qihui WANG, Qingrui HUANG, Jinhe LI
  • Publication number: 20240178228
    Abstract: A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Iuliana Radu
  • Patent number: 11997226
    Abstract: The present disclosure relates to a cover plate, a display panel and a display terminal. The cover plate includes a first region and a second region surrounding the first region. The second region includes a plurality of side cover plate regions and at least one corner opening region located between two adjacent side cover plate regions. The cover plate includes at least one buffer portion which is filled in the corner opening region.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: May 28, 2024
    Assignee: YUNGU (GU'AN) TECHNOLOGY CO., LTD.
    Inventors: Liuyang Wang, Qi Shan, Liwei Ding, Fu Liao, Yuhua Wu, Hongqi Hou, Jun Wang
  • Patent number: 11997935
    Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 28, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11996298
    Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240170437
    Abstract: A package structure is disclosed. The package structure includes a first substrate, a second substrate, a gap, and a directing structure. The second substrate is disposed under the first substrate. The gap is between the first substrate and the second substrate. The gap includes a first region and a second region. The first region is configured to accommodate a filling material. The directing structure is disposed in a flow path of the filling material and configured to reduce a migration of the filling material from the first region to the second region.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Fu KUO, Shang Min CHUANG, Ching Hung CHUANG, Hsu Feng TSENG, Jia Zhen WANG
  • Publication number: 20240167888
    Abstract: In an indoor environment on fire, automatic deployment of sensors disposed on, beneath or over the floor to look upward the ceiling to observe a body of smoke and flame risen near the ceiling allows important information regarding states and dynamics of the body of smoke and flame to be gathered at an early stage of fire (e.g. before arrival of firefighters). By distributing the sensors over the indoor environment, the states and dynamics of the body of smoke and flame are monitored holistically (i.e. as a whole) even at the early stage of fire. Such information is useful to predict development of the fire. In one implementation, a sensor is held in an infrastructure sensor holder mounted on the ceiling during normal time. Upon detecting occurrence of fire, the sensor drops from the holder to land on the floor and orients a sensing direction vertically upward to perform monitoring.
    Type: Application
    Filed: December 5, 2023
    Publication date: May 23, 2024
    Inventors: Qixin WANG, Xinyan HUANG, Muhammad SHAHEER, Tamzid MOHAMMAD, Xiaoning ZHANG, Mingchun LUO, Li-Ta HSU, Xiqiang WU, Fu XIAO, Asif USMANI
  • Publication number: 20240164224
    Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.
    Type: Application
    Filed: December 16, 2022
    Publication date: May 16, 2024
    Inventors: Kai-Jiun CHANG, Yu-Huan YEH, Chuan-Fu WANG
  • Patent number: 11984442
    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 14, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Patent number: 11984478
    Abstract: A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu Wen Wang, Chih-Teng Liao, Chih-Shan Chen, Jui Fu Hsieh, Dave Lo
  • Patent number: 11984164
    Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu
  • Publication number: 20240152162
    Abstract: An aircraft system includes an aircraft, which further includes at least one propeller to provide a flight power for the aircraft; a communication interface configured to communicate with a parachute; at least one storage medium, storing at least one set of instructions for controlling the aircraft system; and at least one processor in communication with the at least one memory. when the aircraft system is in operation, the at least processor executes the at least one set of instruction to: obtain a propeller locking instruction of the aircraft, and perform a corresponding operation based on the propeller locking instruction. The corresponding operation include a first operation. The first operation, corresponds to a scenario where the aircraft is in a flight state, includes: in response to the propeller locking instruction, the aircraft controlling the at least one propeller to stop and locking the at least one propeller, and deploying the parachute by the aircraft.
    Type: Application
    Filed: December 15, 2023
    Publication date: May 9, 2024
    Applicant: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Kai WANG, Peilu SI, Fu LI
  • Publication number: 20240148129
    Abstract: A mobile device attachment adapted for a mobile device and a container for food or liquid is provided. The mobile device attachment includes a magnetic connecting member and a connecting member. The magnetic connecting member is selectively magnetically connected to the mobile device and adapted to extend in an escaping direction. The connecting member is disposed between the container and the magnetic connecting member. The mobile device has an image capturing range. When the magnetic connecting member extends in the escaping direction, the container, the magnetic connecting member and the connecting member are located outside the image capturing range. Besides, a container including the mobile device attachment is also provided.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 9, 2024
    Inventors: CHING-FU WANG, CHING-YU WANG, CHE-WEI HSU, JUI-CHEN LU, CHENG-CHE HO
  • Publication number: 20240154065
    Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in a
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Chien-Chih LIAO, Tzu-Yao TSENG, Tsun-Kai KO, Chien-Fu SHEN