Patents by Inventor Fu-Wei Chen
Fu-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002684Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.Type: GrantFiled: November 21, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
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Publication number: 20240162088Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.Type: ApplicationFiled: January 25, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
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Patent number: 11968817Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.Type: GrantFiled: February 28, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
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Publication number: 20240114810Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.Type: ApplicationFiled: April 20, 2023Publication date: April 4, 2024Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
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Publication number: 20240071799Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: CHUAN WEI LIN, FU-HSIEN LI, YONG-JYU LIN, RONG-SHEN CHEN, CHI-FENG TUNG, HSIANG YIN SHEN
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Patent number: 11915936Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.Type: GrantFiled: January 11, 2023Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wei Su, Fu-Ting Yen, Ting-Ting Chen, Teng-Chun Tsai
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Patent number: 10709255Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.Type: GrantFiled: October 30, 2018Date of Patent: July 14, 2020Assignee: APEX MEDICAL CORP.Inventors: David Huang, Wen-Bin Shen, Ju-Chien Cheng, Ming-Heng Hsieh, Fu-Wei Chen, Chih-Kuang Chang, Yi-Ling Liu, Sheng-Wei Lin, Chung-Yi Lin
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Publication number: 20190142180Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.Type: ApplicationFiled: October 30, 2018Publication date: May 16, 2019Inventors: DAVID HUANG, WEN-BIN SHEN, JU-CHIEN CHENG, MING-HENG HSIEH, FU-WEI CHEN, CHIH-KUANG CHANG, YI-LING LIU, SHENG-WEI LIN, CHUNG-YI LIN
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Apparatus of three-dimensional integrated-circuit chip using fault-tolerant test through-silicon-via
Patent number: 9304167Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.Type: GrantFiled: March 14, 2014Date of Patent: April 5, 2016Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Ting-Ting Hwang, Fu-Wei Chen -
Apparatus of Three-Dimensional Integrated-Circuit Chip Using Fault-Tolerant Test Through-Silicon-Via
Publication number: 20150185274Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.Type: ApplicationFiled: March 14, 2014Publication date: July 2, 2015Applicant: National Tsing Hua UniversityInventors: Ting-Ting Hwang, Fu-Wei Chen -
Publication number: 20120023549Abstract: A method for inviting a challenged entity to provide input concerning a sinograph includes displaying, to the challenged entity, a first region having an image of a challenge sinograph; displaying at least a first event-sensitive region, the first event-sensitive region having an image of a real root of the challenge sinograph; and displaying at least a second event-sensitive region. The second event sensitive region has an image of a faux root of the challenge sinograph.Type: ApplicationFiled: July 21, 2011Publication date: January 26, 2012Applicant: Academia SinicaInventors: Ling-Jyh Chen, Der-Ming Juang, Wen-Yuan Zhu, Hsiao-Hsuan Yu, Fu-Wei Chen
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Patent number: 7633905Abstract: Calibrating a transmit diversity device includes establishing diversity parameter values of diversity parameters for a plurality of signals, where each signal is transmitted from a channel of the transmit diversity device. The following are performed for each diversity parameter value to yield associations: determining a modification parameter value that yields a diversity parameter value, where a modification parameter value describes modulation of a feature of at least one signal; and associating the modification parameter value with the diversity parameter value to yield an association. Calibration data is generated in accordance with the associations.Type: GrantFiled: November 18, 2005Date of Patent: December 15, 2009Assignee: Magnolia Broadband Inc.Inventors: Haim Harel, Yair Karmi, Phil Fu-Wei Chen, Kenneth A. Kludt
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Patent number: 7630445Abstract: Establishing slot boundaries includes receiving a feedback signal reflecting feedback information describing a signal modified according to a diversity parameter adjustment. The feedback signal includes slots and bits. A slot boundary is established for each of the slots by: partitioning the bits into periods; comparing the bits of each period; and establishing the slot boundaries in accordance with the comparison.Type: GrantFiled: October 25, 2005Date of Patent: December 8, 2009Assignee: Magnolia Broadband Inc.Inventors: Yair Karmi, Phil Fu-Wei Chen
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Patent number: 6611756Abstract: A method for enhancing data wipeoff by predicting future navigation data. Data wipeoff using predicted future navigation data reduces or eliminates incomplete data wipeoff, thereby enhancing GPS receiver sensitivity and reducing acquisition times. Predicting future navigation data involves receiving navigation data and using the received navigation data to generate predicted future navigation data, wherein the predicted future navigation data should be approximately identical to navigation data received at a future time. The predicted future navigation data is subsequently used to perform data wipeoff.Type: GrantFiled: August 10, 2000Date of Patent: August 26, 2003Assignee: Lucent Technologies Inc.Inventors: Phil Fu-Wei Chen, Andrew Todd Zidel