Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

Abstract: The invention provides an intra-needle ultrasound system and its method of use for analysis, tracking, and display of pleura in millimeter-scale resolution. This method includes the following steps: Assembling the puncture needle and intra-needle ultrasound transducer, which can generate and receive ultrasound waves at the needle tip. To transform the axial ultrasonic signal into a figure, that can help to identify different anatomic structures according to the corresponding feature of ultrasonic RF (Radio Frequency) signal, and to set the region of interest according to corresponding RF feature of amplitude and depth. This invention can indicate the distance between the ultrasound needle tip and pleura in a real-time fashion, and to identify the best position for anesthetic injection in the paravertebral block (PVB) and the intercostals nerve block (ICNB). The system can also help to avoid damage to the pleura and lung during the nerve block procedure.

Abstract: The invention provides an intra-needle ultrasound system and its method of use for analysis, tracking, and display of pleura in millimeter-scale resolution. This method includes the following steps: Assembling the puncture needle and intra-needle ultrasound transducer, which can generate and receive ultrasound waves at the needle tip. To transform the axial ultrasonic signal into a figure, that can help to identify different anatomic structures according to the corresponding feature of ultrasonic RF (Radio Frequency) signal, and to set the region of interest according to corresponding RF feature of amplitude and depth. This invention can indicate the distance between the ultrasound needle tip and pleura in a real-time fashion, and to identify the best position for anesthetic injection in the paravertebral block (PVB) and the intercostals nerve block (ICNB). The system can also help to avoid damage to the pleura and lung during the nerve block procedure.