Abstract: An intelligent air purifier includes a machine body, a mobile unit, at least one sensor, and a control unit. The machine body has an air inlet, a consumable substance, and an air outlet. The air is sucked from the air inlet, purified by the consumable substance, and discharged from the air outlet. The mobile unit is mounted to the machine body. The sensor is disposed on the machine body for detecting an air quality index of the air in a room. The control unit is communicated with the mobile unit and the senor through electrical signals. The control unit is preset with a pollution value. When the air quality index of the air at a position in the room is greater than the pollution value, the control unit controls the mobile unit to move the machine body to the position to purify the air.

Abstract: A temperature power generation device includes a temperature reactive layer made of high thermal energy absorbing material and a thermal electron generation layer made of low work function material. A temperature power generation method by using the temperature reactive layer and the thermal electron generation layer to absorb heat and generate thermal electrons which are then induced to a conductive layer through an externally applied electric field, and the generated thermal electrons are then further transferred via an electricity output component to an output load for providing power.

Abstract: A temperature power generation device includes a temperature reactive layer made of high thermal energy absorbing material and a thermal electron generation layer made of low work function material. A temperature power generation method by using the temperature reactive layer and the thermal electron generation layer to absorb heat and generate thermal electrons which are then induced to a conductive layer through an externally applied electric field, and the generated thermal electrons are then further transferred via an electricity output component to an output load for providing power.

Abstract: A pillar nonvolatile memory layout methodology includes an arrangement of multiple pillar transistors spaced at intervals on a chip; surrounded in sequence by a SiO2 layer, a floating gate, a dielectric, and a control gate; a separation layer being formed between any two abutted pillar transistors; one up two surfaces of each pillar transistor being connected with a word line and a bit line at right angle to each other; and the word line and the control gate of the pillar transistor being connected to each other while the bit line and the drain being connected to each other respectively and independently as the bit line and the word line being vertical to each other to separate and insulate each pillar transistor for providing one up to four-bit data storage capacity.

Abstract: The present invention disclosed a silicon barrier capacitor device structure. By applying CVD or PVD technologies to deposit poly-silicon layers as the dielectric of capacitor on the doping region of the wafer, then implant a high-density (1016˜1021/cm3) impurity of the group III or group V elements and oxygen ion or nitrogen ion to the poly-silicon layer. After implantation, deposit a low resistance and high melting point conductor on the poly-silicon layer for the electrode. to form a capacitor structure, or repeat all of the deposition poly-silicon and both of the low resistance and high melting point conductor on the poly-silicon layer more than once. All of the odd electrodes are connected together. The even electrodes and the substrate are connected together, too. At last, apply high temperature furnace annealing to the devices. The grain boundary of the silicon was oxidized by oxygen and nitrogen to form an isolation film to be the insulation film.

Abstract: The present invention disclosed a silicon barrier capacitor device structure. By applying CVD or PVD technologies to deposit poly-silicon layers as the dielectric of capacitor on the doping region of the wafer, then implant a high-density (1016˜1021/cm3) impurity of the group III or group V elements and oxygen ion or nitrogen ion to the poly-silicon layer. After implantation, deposit a low resistance and high melting point conductor on the poly-silicon layer for the electrode. to form a capacitor structure, or repeat all of the deposition poly-silicon and both of the low resistance and high melting point conductor on the poly-silicon layer more than once. All of the odd electrodes are connected together. The even electrodes and the substrate are connected together, too. At last, apply high temperature furnace annealing to the devices. The grain boundary of the silicon was oxidized by oxygen and nitrogen to form an isolation film to be the insulation film.

Abstract: The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of fourth bit lines joined to the second bit lines.

Abstract: A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.

Abstract: A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.

Abstract: A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.

Abstract: The mask ROM of the present is comprises by a plurality of word lines arranged in a grid, a plurality of memory units arranged between the word lines, each memory unit having a drain corresponding, a plurality of first bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of second bit lines arranged in parallel and extending in a direction diagonal to the word lines and above the drains, a plurality of first nodes alternately arranged on the first bit lines, a plurality of second nodes alternately arranged on the second bit lines and the second nodes and the first nodes are arranged alternately; a plurality of third bit lines joined to the first bit lines, and a plurality of forth bit lines joined to the second bit lines.

Abstract: A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.

Abstract: An EEPROM memory cell with high radiation resistance is provided. The present EEPROM memory cell comprises a semiconductor substrate of a first conductivity, a source having a region of the semiconductor substrate doped to have a second conductivity opposite to the first conductivity, a drain spaced from the source and having a region of the semiconductor substrate doped to have the second conductivity, a channel formed in the space between the source and the drain within the semiconductor substrate, a first oxide layer with a first thickness overlying and covering the channel of the semiconductor substrate, a conducting charge trapping layer formed on the first oxide layer, a second oxide layer with a second thickness more than the first thickness of the first oxide layer, overlying and covering the conducting charge trapping layer and a conducting gate layer formed on the second oxide layer.

Abstract: A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.

Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

Abstract: A substrate is first provided, and a first oxide layer is formed on the surface of the substrate. A rapid thermal nitrifying (RTN) process anneals the first oxide layer and simultaneously nitrifies the surface of the first oxide layer. Then, a low-pressure chemical vapor deposition (LPCVD) process forms a nitride layer on the surface of the first oxide layer. Finally, a second oxide layer is formed on the surface of the nitride layer. The second oxide layer, the nitride layer and the first oxide layer together construct the ONO layer.

Abstract: A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.

Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

Abstract: A non-volatile flash memory cell with an application of the DIBL phenomenon is provided and comprises following elements: channel region, control gate, and floating gate. The channel region is located under surface of substrate and between source and drain. The control gate is located over the channel region and insulated to the channel region, and width of the control gate is less than width of the channel region. The floating gate is located between the channel region and the control gate and simultaneously insulated to each other, and a width of the floating gate is less than a width of the channel region and the channel region is not totally covered by the control gate and the floating gate. Besides, the control gate and the floating gate are approximately parallel and a bottom of the control gate is more far from the substrate than a top of the floating gate.

Abstract: A method for forming a nonvolatile memory with optimum bias condition is disclosed. Initially, an ONO structure is formed on the substrate wherein the ONO structure has a first oxide layer, a nitride layer and a second oxide layer. Afterwards, a plurality of openings is formed on the ONO structure and a portion of substrate is exposed. An optimum condition of a nonvolatile memory cell having a threshold voltage region wherein the threshold voltage region can be optimum by adjusting a lateral electric field between a drain and a gate to transfer a plurality of electrons into the ONO structure. Thereafter, an implant process is performed to form a plurality of bit lines on substrate. An oxide layer is formed on bit lines to create a bit lines oxide layer. Finally, a polysilicon is formed on bit lines oxide layer and the ONO structure to produce the nonvolatile memory cell.