Abstract: A semiconductor device includes a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect.

Abstract: The present disclosure provides a semiconductor device including: a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect.

Abstract: A plurality of internal circuits (11 to 14) are formed on a semiconductor chip 10, and receive different power supply voltages. An ESD protection circuit (15) is connected to the power supply lines (31 to 34) for the internal circuits (11 to 14). The area in which the protection circuit (15) is formed is closer to the center of the semiconductor chip (10) than the areas for the internal circuits (11 to 14). Surge voltages applied to the power supply pads reach the protection circuit before reaching the reaching the internal circuits.

Abstract: A semiconductor thyristor device includes a semiconductor substrate, two transistors each of which is different junction type from the other and which are provided adjacent to each other in the semiconductor substrate to constitute one thyristor element, a first wiring layer that is formed on the semiconductor substrate and provides a ground potential to one of the transistors, and a second wiring layer that is formed on the semiconductor substrate and provides a power source potential to the other of the transistors. The first wiring layer covers a region in the semiconductor substrate in which the two transistors adjoin each other. This avoids a leakage current that might be generated due to any potential of a wiring layer for another circuit in a chip layout.

Abstract: A plurality of internal circuits (11 to 14) are formed on a semiconductor chip 10, and receive different power supply voltages. An ESD protection circuit (15) is connected to the power supply lines (31 to 34) for the internal circuits (11 to 14). The area in which the protection circuit (15) is formed is closer to the center of the semiconductor chip (10) than the areas for the internal circuits (11 to 14). Surge voltages applied to the power supply pads reach the protection circuit before reaching the reaching the internal circuits.