Patents by Inventor Fumiaki Fujii

Fumiaki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953744
    Abstract: An optical fiber ribbon comprises a plurality of optical fibers arranged in parallel and a connecting resin layer containing a ribbon resin for coating and connecting the plurality of optical fibers, wherein each of the plurality of optical fibers has an outer diameter of 220 ?m or less; and the ribbon resin contains a cured product of urethane (meth)acrylate, and an amount of silicon is 5 ppm or more and 80000 ppm or less and an amount of tin is 5 ppm or more and 30000 ppm or less at the surface of the connecting resin layer.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: April 9, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Noriaki Iwaguchi, Takashi Fujii, Fumiaki Sato
  • Patent number: 9240237
    Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 19, 2016
    Assignee: NAGASE & CO., LTD.
    Inventors: Kanji Otsuka, Yoichi Sato, Yutaka Akiyama, Fumiaki Fujii, Tatsuya Nagasawa, Minoru Uwai
  • Publication number: 20150070957
    Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.
    Type: Application
    Filed: December 26, 2013
    Publication date: March 12, 2015
    Inventors: Kanji Otsuka, Yoichi Sato, Yutaka Akiyama, Fumiaki Fujii, Tatsuya Nagasawa, Minoru Uwai
  • Patent number: 4737864
    Abstract: A still picture reproducing system for a magnetic recording and reproducing apparatus is disclosed. The system sends one frame in order to shift a reproduction mode from ordinary reproduction to reproduction of a still picture by use of so-called "fine slow", sends one more frame if a noise is detected on a picture at this time, and stops if no noise is detected.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: April 12, 1988
    Assignees: Hitachi Microcomputer Eng. Co., Hitachi Video Eng., Hitachi Ltd.
    Inventors: Masataka Sekiya, Hideo Nishijima, Kaneyuki Okamoto, Isao Fukushima, Fumiaki Fujii, Katsumi Sera, Takashi Furutani
  • Patent number: 4707654
    Abstract: An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.
    Type: Grant
    Filed: September 6, 1985
    Date of Patent: November 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Toshiro Suzuki, Fumiaki Fujii, Izuru Yamada
  • Patent number: 4620239
    Abstract: A retrieval signal recording apparatus for magnetic recording/reproducing apparatus wherein when an information signal is recorded on a magnetic tape, a retrieval signal different from the information signal is recorded at the beginning of the recorded information signal so that the magnetic tape is stopped or made in the reproducing mode just when the retrieval signal is picked up from the tape under a high tape speed. In the retrieval signal recording apparatus, the retrieval signal is recorded for a certain time only at the beginning of recording the signal or at both the beginning and end of the recorded signal, and the recording time of the retrieval signal is changed in accordance with the switching of a plurality of tape speeds such that the length of the retrieval signal recorded on the magnetic tape is made substantially constant even if the tape speed is different.
    Type: Grant
    Filed: March 14, 1984
    Date of Patent: October 28, 1986
    Assignee: Hitachi, Ltd.
    Inventor: Fumiaki Fujii
  • Patent number: 4562408
    Abstract: An amplifier comprising a pair of differential input MISFETs, a current mirror circuit connected between the drains of the differential input MISFETs and a power source terminal, a phase compensation circuit connected to the drain of one of the differential input MISFETs, an output stage amplification circuit amplifying the signal produced at the drain of one of the differential input MISFETs, a phase regulation circuit such as a capacitor connected to the other of the differential input transistors, and a feedback circuit feeding back the output signal produced from the output stage amplification circuit to the other of the differential input MISFETs in order to apply negative feedback to the amplifier. Since the capacitor is provided, the phase of the power source noise can be made substantially equal to the phase of noise occurring at the drain of one of the differential input MISFETs due to the power source noise. Hence, hardly any noise is produced from the output stage amplification circuit.
    Type: Grant
    Filed: December 13, 1983
    Date of Patent: December 31, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Nagai, Fumiaki Fujii
  • Patent number: 4507792
    Abstract: In a PCM encoder, in order to reduce noise in an idle channel or in the absence of any voice signal, a detector circuit is provided which detects the idle channel, and a circuit is connected to the detector circuit which fixes the polarity bit of the PCM signal produced by the PCM encoder when the detector circuit has detected the idle channel.
    Type: Grant
    Filed: March 18, 1983
    Date of Patent: March 26, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Yamakido, Shiro Hagiwara, Fumiaki Fujii