Abstract: The cell balance circuit is a circuit connected in parallel to a secondary battery including a battery pack in which a first cell to an nth cell (n is plural) are connected in series in order from a positive electrode to a negative electrode and adjusting individual voltages of n cells. The cell balance circuit includes a switch circuit which can respectively open/close paths connected to n cells, and a cell discharge resistor respectively connected to the first cell to the nth cell via the switch circuit. The switch circuit switches to a cell balance stop state where each of the first cell to the nth cell is not connected to the cell discharge resistor in at least one state of a state where a charger is not connected to an external terminal, or a state where the secondary battery is being discharged to a load.

Abstract: The charge control circuit includes a cell connection detection circuit monitoring a voltage between input ports to which terminals of a cell pack are connected, an overvoltage detection circuit monitoring an overvoltage of the secondary cells, a first latch circuit receiving a signal output by the cell connection detection circuit, a second latch circuit receiving a signal output by the overvoltage detection circuit, a reset circuit outputting a signal to the first latch circuit and the second latch circuit when the charge control circuit is activated, and a control circuit receiving a signal output from the second latch circuit and outputting a signal for protecting the cell pack from the overvoltage. The control circuit does not output a signal for blowing the fuse until the first latch circuit receives a detection signal of the cell connection detection circuit.

Abstract: There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.

Abstract: A charge-discharge control circuit includes a positive power-supply terminal; a negative power-supply terminal; a charge-discharge discrimination circuit which discriminates a discharging state in which a discharging current flows and a charging state in which a charging current flows based on a voltage at a charge-discharge path and a preset charge-discharge discrimination voltage; and a control circuit which turns on a discharge control FET and a charge control FET in a charge-inhibition state and the discharging state or turns off the charge control FET in the charge-inhibition state and the charging state.

Abstract: Provided is a charge/discharge control circuit for controlling charging and discharging of a secondary cell. The charge/discharge control circuit includes a positive power supply terminal and a negative power supply terminal configured to monitor a voltage of the secondary cell, a charge control signal output terminal from which a charge control signal is output, the charge control signal controlling stopping and allowing charging of the secondary cell, a discharge control signal output terminal, an overcurrent detection terminal, an overcurrent cancel terminal, an external voltage input terminal provided separately from the overcurrent cancel terminal, a discharge overcurrent detection circuit connected to the overcurrent detection terminal, to which a discharge overcurrent detection voltage is set, and a discharge overcurrent cancel circuit connected to the overcurrent cancel terminal, to which a discharge overcurrent cancel voltage is set.

Abstract: A charge/discharge control device and a battery apparatus which are compatible with a quick-chargeable charging device which changes a charging current stepwise, the charge/discharge control device and a battery apparatus include an alarm output circuit connected to a control circuit, and a timer circuit which counts a preset period according to an output of an alarm signal from the alarm output circuit and supplies a signal which inhibits the charging to the control circuit after counting the preset period.

Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a control circuit configured to control charge/discharge of the secondary battery; and a power-down release pulse generation circuit connected to the power-down release terminal, the power-down release pulse generation circuit being configured to supply, in a power-down state of the charge/discharge control circuit, a power-down release pulse at least to the control circuit in response to an input of a power-down release signal to the power-down release terminal to release the power-down state.

Abstract: A charge/discharge control device and a battery apparatus respectively include a discharging-overcurrent-detection circuit which monitors a discharging overcurrent according to a discharging-overcurrent-reference voltage based on the voltage of a discharging-overcurrent-detection terminal, and the voltage of a discharge-reference FET having a drain and a gate connected to those of a charge control FET.

Abstract: A charge-discharge control circuit includes a positive power-supply terminal; a negative power-supply terminal; a charge-discharge discrimination circuit which discriminates a discharging state in which a discharging current flows and a charging state in which a charging current flows based on a voltage at a charge-discharge path and a preset charge-discharge discrimination voltage; and a control circuit which turns on a discharge control FET and a charge control FET in a charge-inhibition state and the discharging state or turns off the charge control FET in the charge-inhibition state and the charging state.

Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a charge control terminal connected to a discharge control switch and a charge control switch; a detection terminal; a control circuit; and an output circuit configured to output a charge control signal from the charge control terminal, and configured to output a first voltage when a charger is connected and the control circuit permits charging, and to output a voltage of the detection terminal which differs from the first voltage when the charger is connected and the control circuit prohibits charging. The output circuit is capable of outputting a voltage of the second power supply terminal which differs from the first voltage when the charger is not connected.

Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.

Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.

Abstract: A charge/discharge control device and a battery apparatus respectively include a discharging-overcurrent-detection circuit which monitors a discharging overcurrent according to a discharging-overcurrent-reference voltage based on the voltage of a discharging-overcurrent-detection terminal, and the voltage of a discharge-reference FET having a drain and a gate connected to those of a charge control FET.

Abstract: There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.

Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a charge control terminal connected to a discharge control switch and a charge control switch; a detection terminal; a control circuit; and an output circuit configured to output a charge control signal from the charge control terminal, and configured to output a first voltage when a charger is connected and the control circuit permits charging, and to output a voltage of the detection terminal which differs from the first voltage when the charger is connected and the control circuit prohibits charging. The output circuit is capable of outputting a voltage of the second power supply terminal which differs from the first voltage when the charger is not connected.

Abstract: A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a control circuit configured to control charge/discharge of the secondary battery; and a power-down release pulse generation circuit connected to the power-down release terminal, the power-down release pulse generation circuit being configured to supply, in a power-down state of the charge/discharge control circuit, a power-down release pulse at least to the control circuit in response to an input of a power-down release signal to the power-down release terminal to release the power-down state.

Abstract: Provided is a battery device high in safety and ease of use, which has no difficulty in returning to a normal state after discharge overcurrent is detected. The battery device includes a first charge/discharge control device including a first charge/discharge control transistor, and a first charge/discharge control circuit configured to detect the voltage of a secondary battery to control charging and discharging; a second charge/discharge control device including a second charge/discharge control transistor connected to an external terminal via the first charge/discharge control transistor, and a second charge/discharge control circuit configured to detect the voltage of the secondary battery to control charging and discharging; and a switch circuit arranged between an overcurrent detection terminal of the second charge/discharge control circuit and the external terminal. The switch circuit is turned on with a discharge stopping signal of the second charge/discharge control circuit.

Abstract: Provided is a battery device having high overcurrent detection current accuracy that suppresses increases in a resistance value of a charge/discharge path and in a manufacturing cost. A first charge/discharge control device is configured to monitor a charge/discharge current with a voltage generated across both ends of a charge/discharge control switch, and a second charge/discharge control device is configured to monitor the charge/discharge current with a voltage generated across both ends of a current sensing resistor. A field effect transistor forming the charge/discharge control switch is selected based on a desired ON resistance value. The charge/discharge control switch of the first charge/discharge control device includes a field effect transistor having the desired ON resistance value, and a charge/discharge control switch of the second charge/discharge control device includes a field effect transistor having an ON resistance value other than the desired ON resistance value.

Abstract: Provided is a charge/discharge control circuit for controlling charging and discharging of a secondary cell. The charge/discharge control circuit includes a positive power supply terminal and a negative power supply terminal configured to monitor a voltage of the secondary cell, a charge control signal output terminal from which a charge control signal is output, the charge control signal controlling stopping and allowing charging of the secondary cell, a discharge control signal output terminal, an overcurrent detection terminal, an overcurrent cancel terminal, an external voltage input terminal provided separately from the overcurrent cancel terminal, a discharge overcurrent detection circuit connected to the overcurrent detection terminal, to which a discharge overcurrent detection voltage is set, and a discharge overcurrent cancel circuit connected to the overcurrent cancel terminal, to which a discharge overcurrent cancel voltage is set.

Abstract: There is provided a battery device in which the accuracy of an over-current detection current value is high to have high safety. In a charging/discharging control circuit, a reference voltage circuit of an over-current detection circuit is configured to include a constant current circuit, a resistor, and a transistor having a resistance value that varies with a voltage of a secondary cell, that are connected to both ends of the secondary cell, and outputs, as a reference voltage, a voltage that is generated due to the flowing of a current of the constant current circuit to the resistor and the transistor.