Abstract: A control device is provided that controls a connection between a specific one of a plurality of arithmetic processors and a specific one of a plurality of main memory units in accordance with an access request supplied from the specific arithmetic processor. The access request has request tag information. A buffer section buffers the request tag information in response to a write-in address. A supplying section supplies the specific main memory unit with an additional access request having the write-in address as an identifier instead of the request tag information. When the specific main memory access ends, the specific memory unit supplies the control device with a reply signal having the identifier as a reply identifier. A read section reads the request tag information out of the buffer section in accordance with the reply identifier. The request tag information is delivered from the control device to the specific arithmetic processor.

Abstract: An address translation buffer control system includes multiple prioritized address translation buffers and circuitry for changing the contents of the buffers. When a desired address translation pair is not present in the buffer having the highest priority, the contents of the highest priority buffer are replaced with contents from a lower priority buffer. If a desired address translation pair is not present in any buffer, the contents of the lowest priority buffer are replaced.