Patents by Inventor Fumihiko Momose
Fumihiko Momose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387062Abstract: A semiconductor device encompasses a mounting member having a copper-based wiring layer; first covering layer which contains nickel, covering the wiring layer so that a part of upper surface of the wiring layer is exposed in opening; joint layer metallurgically joined to the wiring layer in the opening; second covering layer which contains nickel, metallurgically joined to the joint layer on upper surface of the joint layer; semiconductor chip having bottom surface covered with the second covering layer. The joint layer has lower layer in contact with the wiring layer, upper layer in contact with the second covering layer, and intermediate layer between the lower layer and the upper layer, the lower layer and the upper layer have intermetallic compounds as main components which contain tin, copper and nickel, and the intermediate layer is alloy containing tin as the main component and no lead.Type: ApplicationFiled: April 24, 2023Publication date: November 30, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko MOMOSE, Hirohisa OYAMA, Yasuaki HOZUMI
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Publication number: 20230307346Abstract: A method of manufacturing a semiconductor device, includes; preparing an insulated circuit substrate including a circuit layer having a main surface and a side surface inclined to a normal direction of the main surface; irradiating the side surface of the circuit layer with a laser beam so as to roughen at least a part of the side surface of the circuit layer and provide an oxide film on the roughened side surface of the circuit layer; and bonding a semiconductor chip to the main surface of the circuit layer via a solder layer.Type: ApplicationFiled: January 27, 2023Publication date: September 28, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuaki HOZUMI, Fumihiko MOMOSE, Natsuki TAKEISHI, Ryoto UCHIYAMA
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Patent number: 11749581Abstract: Provided are a semiconductor module in which bonding properties between an insulated substrate and a sealing resin is improved and a method for manufacturing the semiconductor module. A semiconductor module 50 is provided with: an insulated substrate 23; a circuit pattern 24 that is formed on the insulated substrate; semiconductor elements 25, 26 that are joined on the circuit pattern; and a sealing resin 28 for sealing the insulated substrate, the circuit pattern, and the semiconductor elements. The surface 23a of the insulated substrate in a part where the insulative substrate and the sealing resin are bonded to each other, is characterized in that, in a cross section of the insulated substrate, the average roughness derived in a 300-?m wide range is 0.15 ?m or greater and the average roughness derived in a 3-?m-wide range is 0.02 ?m or greater.Type: GrantFiled: February 6, 2019Date of Patent: September 5, 2023Assignees: FUJI ELECTRIC CO., LTD., DOWA METAL TECH CO., LTD.Inventors: Yuhei Nishida, Fumihiko Momose, Takashi Ideno, Yukihiro Kitamura
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Publication number: 20220375845Abstract: A semiconductor device, including a sealing body portion, a nut and a bus bar. The sealing body portion has a housing portion formed on a front surface thereof, the sealing body portion including a semiconductor chip contained therein and a plurality of pin-shaped external connection terminals electrically connected to the semiconductor chip. The nut has a screw hole and disposed in the housing portion. The bus bar is arranged opposite the housing portion, and includes a fastening area with an opening portion opposite the screw hole of the nut, and a bonding area that is outside the fastening area and is connected to the plurality of external connection terminals. The sealing body portion has a protrusion adjacent to the bonding area of the bus bar.Type: ApplicationFiled: April 18, 2022Publication date: November 24, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Norihiro DAICHO, Fumihiko MOMOSE
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Publication number: 20210407953Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, an element selected from the group consisting of: more than 0 and 1.0% by mass or less of Si, more than 0 and 0.1% by mass or less of V, 0.001 to 0.1% by mass of Ge, 0.001 to 0.1% by mass of P, and more than 0 and 1.2% by mass or less of Cu, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshitaka NISHIMURA, Fumihiko MOMOSE
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Patent number: 11145615Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.Type: GrantFiled: June 5, 2020Date of Patent: October 12, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
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Patent number: 10896892Abstract: Provided is a wire bonding apparatus for electrically connecting an electrode and an aluminum alloy wire to each other by wire bonding. The apparatus includes a wire feeding device which feeds the wire. The wire has a diameter not less than 500 ?m and not greater than 600 ?m. The apparatus includes a heating device heats the wire to a temperature that is not lower than 50° C. and not higher than 100° C. The apparatus further includes a pressure device which presses the wire against the electrode. The apparatus further includes an ultrasonic wave generating device which generates an ultrasonic vibration that is applied to the wire that is pressed by the pressure device.Type: GrantFiled: March 9, 2015Date of Patent: January 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko Momose, Takashi Saito, Kazumasa Kido, Yoshitaka Nishimura
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Publication number: 20200388553Abstract: Provided are a semiconductor module in which bonding properties between an insulated substrate and a sealing resin is improved and a method for manufacturing the semiconductor module. A semiconductor module 50 is provided with: an insulated substrate 23; a circuit pattern 24 that is formed on the insulated substrate; semiconductor elements 25, 26 that are joined on the circuit pattern; and a sealing resin 28 for sealing the insulated substrate, the circuit pattern, and the semiconductor elements. The surface 23a of the insulated substrate in a part where the insulative substrate and the sealing resin are bonded to each other, is characterized in that, in a cross section of the insulated substrate, the average roughness derived in a 300-?m wide range is 0.15 ?m or greater and the average roughness derived in a 3-?m-wide range is 0.02 ?m or greater.Type: ApplicationFiled: February 6, 2019Publication date: December 10, 2020Inventors: Yuhei NISHIDA, Fumihiko MOMOSE, Takashi IDENO, Yukihiro KITAMURA
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Publication number: 20200303337Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko WATANABE, Shunsuke SAITO, Yoshitaka NISHIMURA, Fumihiko MOMOSE
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Patent number: 10727194Abstract: To provide a lead-free solder the heat resistance temperature of which is high and thermal conductive property of which are not changed in a high temperature range. A semiconductor device of the present invention includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities, and a bonding layer including the solder material, which is formed between a semiconductor element and a substrate electrode or a lead frame.Type: GrantFiled: August 28, 2017Date of Patent: July 28, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
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Patent number: 10497586Abstract: A semiconductor device has a U terminal with an internal joint portion at one end that is joined to a circuit board, an intermediate portion that is embedded in a case, and an external joint portion at another end that is exposed from the case, the U terminal being provided with a shock absorbing portion that is positioned between an inner surface of the case and the internal joint portion and absorbing stress that acts upon the internal joint portion. Due to the presence of the shock absorbing portion, even when the entire semiconductor device deforms or there is local deformation such that stress becomes concentrated at the joined surfaces of the internal joint portion and the circuit board, the stress is absorbed by the shock absorbing portion.Type: GrantFiled: June 16, 2017Date of Patent: December 3, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuta Tamai, Fumihiko Momose
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Patent number: 10297527Abstract: A semiconductor device includes a radiation plate having a rear surface roughened by a plurality of dents that overlap with each other; a laminated substrate provided on a front surface of the radiation plate and including an insulating plate, a circuit board provided on a front surface of the insulating plate, and a metal plate provided on a rear surface of the insulating plate; a semiconductor chip provided on the circuit board; a radiator; and a heat radiating material retained between the rear surface of the radiation plats and the radiator. The plurality of dents that roughen the rear surface of the radiation plate provides the rear surface with an arithmetic average roughness ranging from 1 ?m to 10 ?m, and each of the dents has a maximum dent depth ranging from 12 ?m to 71.5 ?m, and a dent width ranging from 0.17 mm to 0.72 mm.Type: GrantFiled: August 1, 2016Date of Patent: May 21, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takashi Saito, Fumihiko Momose, Yoshitaka Nishimura, Eiji Mochizuki
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Patent number: 10276474Abstract: A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.Type: GrantFiled: April 6, 2016Date of Patent: April 30, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takashi Saito, Ryoichi Kato, Yoshitaka Nishimura, Fumihiko Momose
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Patent number: 10199305Abstract: In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate. In addition, when the small depressions are formed in the first joining region of the back surface of the heat releasing plate, the hardness of the first joining region of the back surface increases. Hence, the scratch is prevented from being created on the back surface of the heat releasing plate on which the depressions are formed to overlap each other in the first joining region of the back surface.Type: GrantFiled: February 28, 2018Date of Patent: February 5, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko Momose, Takashi Saito
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Patent number: 10157877Abstract: A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are Sn crystal grains containing tin and antimony in a predetermined proportion. The second crystal sections (22) are made up of a first portion containing a predetermined proportion of Ag atoms with respect to Sn atoms, or a second portion containing a predetermined proportion of Cu atoms with respect to Sn atoms, or both. The solder joint layer may have third crystal sections (23) which are crystal grains that contain a predetermined proportion of Sb atoms with respect to Sn atoms. As a result, solder joining is enabled at a low melting point, and a highly reliable solder joint layer having a substantially uniform metal structure can be formed.Type: GrantFiled: October 8, 2015Date of Patent: December 18, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kazumasa Kido, Takashi Saitou, Kyouhei Fukuda, Shinji Tada, Fumihiko Momose, Yoshitaka Nishimura
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Patent number: 10090223Abstract: A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 ?m, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.Type: GrantFiled: March 8, 2017Date of Patent: October 2, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko Momose, Hiroyuki Nogawa, Yoshitaka Nishimura, Eiji Mochizuki
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Patent number: 10090222Abstract: A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface.Type: GrantFiled: January 5, 2018Date of Patent: October 2, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Akira Hirao, Eiji Mochizuki, Fumihiko Momose
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Publication number: 20180240730Abstract: A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface.Type: ApplicationFiled: January 5, 2018Publication date: August 23, 2018Applicant: Fuji Electric Co., Ltd.Inventors: Akira HIRAO, Eiji MOCHIZUKI, Fumihiko MOMOSE
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Publication number: 20180190570Abstract: In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate. In addition, when the small depressions are formed in the first joining region of the back surface of the heat releasing plate, the hardness of the first joining region of the back surface increases. Hence, the scratch is prevented from being created on the back surface of the heat releasing plate on which the depressions are formed to overlap each other in the first joining region of the back surface.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Fumihiko MOMOSE, Takashi SAITO
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Patent number: 9978701Abstract: A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 ?m to 7 ?m. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 ?m to 20 ?m.Type: GrantFiled: September 3, 2015Date of Patent: May 22, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takashi Saito, Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura