Abstract: A signal distributing circuit of the invention includes a first element which outputs a first signal and a second signal which is opposite to that of the first signal. The circuit is provided with a first signal line on which the first signal is transmitted and a second signal line on which the second signal is transmitted. A plurality of second elements each of which is connected to the first signal line in a first order and connected to the second signal line in a second order, wherein the second order is opposite to that of the first order. A method for connecting a plurality of loads to first and second signal lines, which are allocated to a regular signal and a signal opposite to that of the regular signal, respectively, of the invention includes connecting the loads to the first signal lines in a first order; and connecting the loads to the second signal lines in an order opposite to that of the first order.

Abstract: A high-level signal is sent to a mode control terminal, a pulse for slew-rate adjustment is sent to a replicated gate, and the slew rate at a measurement terminal is set to a desired value using a switch unit. The slew rate of the replicated gate having the same structure as the structure of output circuits and being formed on the same semiconductor substrate is set based on digital signal which are generated upon operation of the switch unit. The slew rate of output circuits is so adjusted as to be the same as the slew rate of the replicated gate.

Abstract: A bus circuit of this invention has a bus line. A bus input circuit and a bus output circuit are connected to the bus line. The bus line is charged by a precharge circuit. The bus output circuit outputs an output signal to the bus line by discharging or not discharging potential of the bus line. The bus input circuit inputs a signal from the bus line. The bus input circuit includes a feedback circuit which inputs potential of the bus line as the signal, amplifies the signal in accordance with a change of the signal, and feeds back the amplified result to the bus line.

Abstract: An output circuit according to the present invention is provided with a delay circuit for delaying an enable control signal by a predetermined period td and an output means capable of controlling the output state in either an enable or a disable state, wherein the output state of the first output means so controlled as to be switched from the disable to the enable in accordance with the enable control signal and to be switched from the enable to the disable state gradually in accordance with the signal supplied from the first delay circuit.