Abstract: In a semiconductor device, a lower chip includes a first group of connection terminals provided on a straight region including a corner region and a region extending from the corner region along one side. An upper chip includes a second group of connection terminals. The upper chip and the lower chip are arranged so that the first group of connection terminals at least partially overlaps with the second group of connection terminals. The first group of connection terminals is at least partially electrically connected to the second group of connection terminals.

Abstract: In a semiconductor device (1), a lower chip (20) includes a first group of connection terminals (26) provided on a straight region (34) including a corner region (32) and a region extending from the corner region along one side. An upper chip (10) includes a second group of connection terminals (12). The upper chip (10) and the lower chip (20) are arranged so that the first group of connection terminals (26) at least partially overlaps with the second group of connection terminals (12). The first group of connection terminals (26) is at least partially electrically connected to the second group of connection terminals (12).

Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).

Abstract: A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS.

Abstract: A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS.

Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).

Abstract: A photochromic material comprising a styrene-based oligomer having a weight average molecular weight of from 200 to 6000 and a photochromic compound selected from the group consisting of spirooxazine derivatives and spiropyran derivatives.

Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.

Abstract: Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

Abstract: The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.

Abstract: In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then, whether or not an error exists is judged and, among redundant vias located on a signal line in which a design constraint violation has occurred, how many vias have to be converted to single vias, respectively, to avoid the design constraint violation is calculated. In a via conversion step, a redundant via which has caused an error is converted to a single via, based on a result of the calculation. Thus, a design constraint violation regarding an error such as an antenna effect error and a timing constraint violation caused by a redundant via obtained by converting a single via for improving yield hardly occurs.

Abstract: A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS.

Abstract: Prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI is realized. To do this, a contact array is provided in which a plurality of contacts is formed so as to be aligned in the vertical and the horizontal directions. In the contact array, the contact formation spacing in both of the vertical and the horizontal directions is larger than the contact formation spacing determined by the manufacturing process. Consequently, the number of contacts formed in the contact array can be reduced to not more than the number of contacts that can be formed in the unit area determined by the process, so that prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI can be realized.

Abstract: Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

Abstract: A photochromic material comprising a styrene-based oligomer having a weight average molecular weight of from 200 to 6000 and a photochromic compound selected from the group consisting of spirooxazine derivatives and spiropyran derivatives.

Abstract: A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Abstract: Prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI is realized. To do this, a contact array is provided in which a plurality of contacts is formed so as to be aligned in the vertical and the horizontal directions. In the contact array, the contact formation spacing in both of the vertical and the horizontal directions is larger than the contact formation spacing determined by the manufacturing process. Consequently, the number of contacts formed in the contact array can be reduced to not more than the number of contacts that can be formed in the unit area determined by the process, so that prevention of coming off of the layer where the contacts are formed and the isolating film and breakage of the LSI can be realized.

Abstract: Where there are wirings with different film thicknesses or a sheet resistance in a non-scraped state of a wiring layer cannot be obtained as a result of the CPM technique, a wiring resistance according to a film thickness when an LSI is manufactured is acquired by automatic processing to reduce its difference from a real resistance, and accurate voltage drop analysis is carried out to reduce malfunction in a real chip. In a semiconductor circuit device with a plurality of kinds of film thicknesses in the same wiring layer, with a variation occurring in the wiring film thickness when wirings are formed on a silicon wafer, or a warp occurring in an upper layer because the stacking of lower layers is not uniform in the manufacturing process of the wiring, an error of the wiring resistance due to the difference in the film thickness or warp of the wiring is corrected to produce a virtual layout data.

Abstract: A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.