Patents by Inventor Fumihito Inoue

Fumihito Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4795963
    Abstract: In the A/D converter test method, the square wave pulse as the test signal is supplied to the A/D converter under test; said pulse is converted into the digital signal by said A/D converter; the waveform of said square wave pulse is reconstructed by converting the digital signal outputted from said A/D converter into the analog signal; the rise time of said A/D converter under test is measured from the reconstructed waveform of said square wave pulse; and the dynamic characteristics of said A/D converter is calculated from the measured rise time.
    Type: Grant
    Filed: May 1, 1986
    Date of Patent: January 3, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Ueno, Fumio Ikeuchi, Fumihito Inoue
  • Patent number: 4583223
    Abstract: A first signal generator and a second signal generator for setting measuring conditions of a connection pin of a device under test are disposed in each of a number of signal transmission circuits. Each of the signal generators stores therein information for setting a measuring condition in the form of a digital data, which is D-A converted, and this D-A converted output determines the measuring condition. Analog switches are disposed for selecting as a measuring condition of the connection pin either the D-A converted output of the first signal generator or that of the second signal generator. A first discriminator and a second discriminator for discriminating the quality of measured results of the connection pin of the device under test are disposed in each of the signal transmission circuits.
    Type: Grant
    Filed: March 14, 1983
    Date of Patent: April 15, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Inoue, Yuichi Ohyama, Kinichi Nakahara, Kazuhiko Kimura
  • Patent number: 4025802
    Abstract: In a capacitance circuit having a capacitance element which exhibits a breakdown characteristic and which generates noises at breakdown, the improvement comprising a constant-voltage element, which has a lower breakdown voltage than the capacitance element and a lower noise level than the capacitance element in the state of breakdown, connected in parallel with the capacitance element. The voltage across the capacitance element is clamped at the breakdown voltage of the constant-voltage element, so that the capacitance element is prevented from breaking down and thus generating noise components.
    Type: Grant
    Filed: July 17, 1975
    Date of Patent: May 24, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Inoue, Yoshiji Nakajima, Noboru Horie
  • Patent number: 3962718
    Abstract: In a capacitance circuit having a capacitance element which exhibits a breakdown characteristic and which generates noises at breakdown, the improvement comprising a constant-voltage element, which has a lower breakdown voltage than the capacitance element and a lower noise level than the capacitance element in the state of breakdown, connected in parallel with the capacitance element. The voltage across the capacitance element is clamped at the breakdown voltage of the constant-voltage element, so that the capacitance element is prevented from breaking down and thus generating noise components.
    Type: Grant
    Filed: October 4, 1973
    Date of Patent: June 8, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Fumihito Inoue, Yoshiji Nakajima, Noboru Horie