Patents by Inventor Fumikazu Takei
Fumikazu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10141295Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: October 12, 2017Date of Patent: November 27, 2018Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20180040598Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: October 12, 2017Publication date: February 8, 2018Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
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Patent number: 9825017Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: September 19, 2016Date of Patent: November 21, 2017Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20170005080Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
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Patent number: 9490218Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: May 12, 2015Date of Patent: November 8, 2016Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Patent number: 9230938Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: GrantFiled: December 27, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
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Publication number: 20150243605Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: May 12, 2015Publication date: August 27, 2015Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Patent number: 9053954Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: March 3, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20150111317Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: ApplicationFiled: December 27, 2014Publication date: April 23, 2015Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
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Patent number: 8945953Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: GrantFiled: December 18, 2013Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
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Publication number: 20140287541Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: March 3, 2014Publication date: September 25, 2014Applicant: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20140179032Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: ApplicationFiled: December 18, 2013Publication date: June 26, 2014Applicant: Renesas Electronics CorporationInventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi