Abstract: A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

Abstract: A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

Abstract: A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

Abstract: A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

Abstract: A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: A semiconductor integrated circuit having, for instance, a power source side conductor and an earth side conductor which are constructed such that the two conductors are formed into two layers mutually laminated in parallel, and a dielectric substance is interposed between the two layers for providing a capacitance. In this manner, the integrated circuit is operable such that a comparatively large capacitor is connected in the power source circuit thereof.

Abstract: A dynamic RAM comprises a semiconductor substrate, first and second MOS transistor formed on said semiconductor substrate, each having a source, a drain, and a gate, a first insulation film formed on said first and second MOS transistors, a first electrode formed on said first insulation film, for accumulating an electrical charge, the first electrode extending through a first hole made in the first insulation film and connected to one of the source and drain of said first MOS transistor, a second electrode formed on the first insulation film, for accumulating an electrical charge, the second electrode extending through a second hole made in the first insulation film and connected to one of the source and drain of the second MOS transistor, and at least one part of the second electrode being spaced apart from, located above, and overlapping part of the first electrode, first and second capacitor-insulating films formed on the first and second electrodes, respectively, and a capacitor electrode fromed on the f

Abstract: A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.

Abstract: In a semiconductor memory device, a storage node electrode having a cavity is provided such that the inner surface of a storage node electrode is used as a capacitor electrode. In a DRAM fabricating method, a storage node electrode having a cavity is formed by laminating a first conductor layer, an insulating film and a second conductor layer, which in turn are patterned into a desired shape, depositing a third conductor layer on the three-layer pattern, performing anisotropic etching so as to cause the third conductor layer to remain only on the side walls of the pattern to thereby form a box-shaped conductor, forming an opening in a part of the box-shaped conductor, removing the insulating film by an etching to thereby form a cavity.

Abstract: When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, and forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: An MOS transistor comprises a projection formed on the surface of a semiconductor substrate, a gate insulating film having an upper portion located on the upper surface of the projection and a pair of side portions extending from the upper portion and located on the side surfaces of the projection, source and drain regions located in the projection to sandwich the gate insulating film and to be exposed on the upper surface of the projection, and a gate electrode, having first and second portions respectively formed on the upper and side portions of the gate insulating film, for generating a depletion layer extending deeper into the projection than would a depletion layer generated by only the first portion, in the portion of the projection facing the first portion.

Abstract: A semiconductor device includes a rectangular semiconductor chip, first to fourth memory cell arrays formed on the semiconductor chip, and first to fourth bonding pads formed on the peripheral part of the semiconductor chip. In this semiconductor device in particular, first bonding pads are disposed along a first long side of the semiconductor chip while second bonding pads are disposed along a second long side of the chip. The first and second memory cell arrays are disposed between the first bonding pads and the second long side while the third and fourth memory cell arrays are disposed between the first long side and the second pads.

Abstract: A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.

Abstract: A semiconductor memory device having at least one memory cell array block with a plurality of memory cells formed at the surface of a semiconductor substrate. Each memory cell includes a transistor and memory capacitor. The device further has a plurality of word lines for addressing the memory cells, a plurality of bit lines for reading from and writing to the memory capacitors, at least one cell plate formed on the semiconductor substrate, the cell plate forming a common electrode of the memory capacitors, a cell plate voltage generator for supplying a voltage of a level between the supply voltage and the ground voltage to the cell plate, and a control circuit for controlling the output impedance of the cell plate voltage generating unit.

Abstract: A high-density semiconductor memory with charge-coupling memory cells is disclosed. Each CC cell includes three field effect transistors and one capacitor, which are integrated in a small area by sharing their nodes with one another. A P.sup.+ type semiconductor layer of high-impurity concentration is formed in a shallow N type semiconductive layer and is electrically floating to function as the data storage capacitor. The potential corresponding to the data storage in the above P.sup.+ layer controls the readout current flowing through the N layer.

Abstract: A semiconductor memory device with a refresh mechanism having a plurality of memory cells integrated on a semiconductor substrate, a plurality of word lines and digit lines each connected to the memory cells, a refresh control circuit for successively selecting the word lines and refreshing the memory cells word line by word line in a refresh period and a time constant circuit connected to the word lines. The time constant circuit is activated whenever the word line connected to it is selected during an access period and emits a "refresh not required" signal until a predetermined time has elapsed. The refresh control circuit receives the "refresh not required" signal and then acts so as to skip the refreshing operation.

Abstract: A method for manufacturing a semiconductor device is disclosed which comprises the step of forming one or more first grooves by selectively etching a field region of a semiconductor substrate, the step of forming, on the entire surface of the substrate including the first groove, a first insulating film having a thickness substantially equal to or greater than the depth of the first groove, this first insulating film having on its upper surface one or more second grooves corresponding to the first groove, at least one of the second grooves having a width greater than its depth, the step of selectively forming, in at least one of the second grooves having a width greater than its depth, a second insulating film having a thickness substantially equal to the depth of the second groove, the step of forming a third insulating film having a flat surface on its whole surface, the step of applying an anisotropic dry etching technique to the resultant structure to expose the surface of the substrate, thereby obtaining