Patents by Inventor Fumio Murabayashi
Fumio Murabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6625522Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.Type: GrantFiled: March 9, 2001Date of Patent: September 23, 2003Assignee: Hitachi, Ltd.Inventors: Kohei Sakurai, Nobuyasu Kanekawa, Fumio Murabayashi, Mitsuru Watabe, Toshio Hayashibara
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Patent number: 6590425Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented.Type: GrantFiled: June 25, 2001Date of Patent: July 8, 2003Assignee: Hitachi, Ltd.Inventors: Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, Hiromichi Yamada
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Publication number: 20030117751Abstract: A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pulse signal, which has propagated through an insulating circuit, into the original state signal or a signal having the same characteristics as the original state signal.Type: ApplicationFiled: February 4, 2003Publication date: June 26, 2003Applicant: HITACHI, LTD.Inventors: Fumio Murabayashi, Takashi Sase, Mutsumi Kikuchi, Atsuo Watanabe, Masatsugu Amishiro, Kenji Tabuchi
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Patent number: 6563200Abstract: In an interface device in which by means of a buried insulation film 412 and a region insulation portion 410 an SOI substrate 414 is divided into a semiconductor support substrate region 411, a controller side region 407 and a network side region 408 and a part of isolator circuits 405 and 406 making use of a static capacitance are formed in the network side region 408, the semiconductor support substrate region 411 and the network side region 408 are connected to a network power source to always keep these regions at a same potential, thereby, an interface device using a dielectric isolation substrate which suppresses erroneous operations due to noises and characteristic deterioration, and a system using the same are provided.Type: GrantFiled: August 29, 2001Date of Patent: May 13, 2003Assignee: Hitachi, Ltd.Inventors: Mutsumi Kikuchi, Fumio Murabayashi, Takashi Sase, Atsuo Watanabe, Masatsugu Amishiro
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Patent number: 6538866Abstract: A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.Type: GrantFiled: March 16, 2000Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Keiji Hanzawa, Masahiro Matsumoto, Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Kohei Sakurai, Atsushi Miyazaki
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Patent number: 6539322Abstract: A sensor device is provided which included a digital arithmetic processing unit which performs arithmetic processing through a program stored therein in advance, a pulse generator for generating pulses through the program, and a unit for causing the output voltage of the sensor device to stay at either a power source voltage concerned or the ground voltage, when the pulses from the pulse generator are interrupted, thereby, a sensor device using digital arithmetic processing and outputting analogue voltages is provided allowing the host system to judge easily whether the sensor device is operating normally or is failing.Type: GrantFiled: May 31, 2000Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Masahiro Matsumoto, Kohei Sakurai, Fumio Murabayashi, Hiromichi Yamada, Tatsumi Yamauchi, Atsushi Miyazaki, Keiji Hanzawa
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Patent number: 6489906Abstract: A &Dgr;&Sgr; type AD converter includes a local D/A converter having a SC integrator which is constructed by an analog switch operated at the first and second timings of an input 1, an analog switch operated at the first and second timings of an input 2, an analog switch operated at the first and second timings without selection of the input, a capacitor charged and discharged by these analog switches and an operational amplifier (21), a comparator (22), a D-type flip-flop (28), a switch (29) and reference voltage sources (30, 31).Type: GrantFiled: February 20, 2001Date of Patent: December 3, 2002Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Masahiro Matsumoto, Fumio Murabayashi, Tatsumi Yamauchi, Keiji Hanzawa
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Publication number: 20020175718Abstract: A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.Type: ApplicationFiled: August 17, 2001Publication date: November 28, 2002Inventors: Fumikazu Takahashi, Tatsumi Yamauchi, Fumio Murabayashi, Kazuhisa Miyamoto, Kazuharu Kuchimachi
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Patent number: 6462580Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.Type: GrantFiled: December 28, 2000Date of Patent: October 8, 2002Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
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Publication number: 20020130683Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.Type: ApplicationFiled: May 14, 2002Publication date: September 19, 2002Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
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Patent number: 6437621Abstract: A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.Type: GrantFiled: March 26, 2001Date of Patent: August 20, 2002Assignee: Hitachi, Ltd.Inventors: Kazuo Kato, Takashi Sase, Takashi Hotta, Fumio Murabayashi
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Publication number: 20020105062Abstract: In an interface device in which by means of a buried insulation film 412 and a region insulation portion 410 an SOI substrate 414 is divided into a semiconductor support substrate region 411, a controller side region 407 and a network side region 408 and a part of isolator circuits 405 and 406 making use of a static capacitance are formed in the network side region 408, the semiconductor support substrate region 411 and the network side region 408 are connected to a network power source to always keep these regions at a same potential, thereby, an interface device using a dielectric isolation substrate which suppresses erroneous operations due to noises and characteristic deterioration, and a system using the same are provided.Type: ApplicationFiled: August 29, 2001Publication date: August 8, 2002Inventors: Mutsumi Kikuchi, Fumio Murabayashi, Takashi Sase, Atsuo Watanabe, Masatsugu Amishiro
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Patent number: 6385755Abstract: An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.Type: GrantFiled: July 10, 2000Date of Patent: May 7, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuya Shimomura, Fumio Murabayashi, Kotaro Shimamura, Nobuyasu Kanekawa, Takashi Hotta
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Publication number: 20020050799Abstract: A lighting apparatus capable of improving amenity and energy-saving and controlling a lighting load as a user intends to do. The lighting apparatus is connected to a network and controlling the lighting load corresponding to information from the network, and the lighting apparatus further comprises an automatic mode for controlling the lighting load corresponding to the information from the network, a manual mode for controlling the lighting load independently of the information from the network, and a switching means for switching between the automatic mode and the manual mode.Type: ApplicationFiled: July 27, 2001Publication date: May 2, 2002Inventors: Tatsumi Yamauchi, Fumio Murabayashi, Haruki Komatsu, Akio Inada
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Patent number: 6377480Abstract: In a switching power source comprising a triangular wave generating circuit and an error amplifier and a PWM comparator, in normal time PWM pulses being obtained by comparing an output amplitude of triangular wave of the triangular wave generating circuit with an output voltage of the error amplifier as a reference voltage using the PWM comparator, the soft-start circuit of the switching power source comprises a soft-start reference value setting part composed of a group of resistance networks and a group of switches using the same structure as an upper-and-lower limit setting part, composed of networks and switches, for setting an upper and a lower limits of the amplitude of triangular wave of the triangular generating circuit; and a counting circuit for counting cycles of the triangular wave of the triangular wave generating circuit to obtain a plurality of arbitrary soft-start timings in order to switch the group of switches.Type: GrantFiled: August 14, 2001Date of Patent: April 23, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Sase, Fumio Murabayashi, Mutsumi Kikuchi
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Publication number: 20020029098Abstract: To provide a low-cost vehicle control system and a car using the system by making radiation of an actuator driver easy and thereby reducing the radiation component cost and moreover, downsizing an electronic control unit and improving the versatility.Type: ApplicationFiled: March 9, 2001Publication date: March 7, 2002Applicant: Hitachi Ltd.Inventors: Kohei Sakurai, Nobuyasu Kanekawa, Fumio Murabayashi, Mitsuru Watabe, Toshio Hayashibara
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Publication number: 20010043084Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and a particle noise and noises due to charge redistribution effect or leakage current can be prevented.Type: ApplicationFiled: June 25, 2001Publication date: November 22, 2001Inventors: Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, Hiromichi Yamada
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Publication number: 20010030621Abstract: A &Dgr;&Sgr; type AD converter includes a local D/A converter having a SC integrator which is constructed by an analog switch operated at the first and second timings of an input 1, an analog switch operated at the first and second timings of an input 2, an analog switch operated at the first and second timings without selection of the input, a capacitor charged and discharged by these analog switches and an operational amplifier (21), a comparator (22), a D-type flip-flop (28), a switch (29) and reference voltage sources (30, 31).Type: ApplicationFiled: February 20, 2001Publication date: October 18, 2001Inventors: Masahiro Matsumoto, Fumio Murabayashi, Tatsumi Yamauchi, Keiji Hanzawa
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Publication number: 20010017560Abstract: An object of the present invention is to provide a waveform shaping circuit by which the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency.Type: ApplicationFiled: March 26, 2001Publication date: August 30, 2001Inventors: Kazuo Kato, Takashi Sase, Takashi Hotta, Fumio Murabayashi
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Patent number: 6282136Abstract: In a semiconductor memory device, the drain of a transistor for pre-charging is connected to a data line via the Y switch. Lower level bit signals are input into an X decoder for selecting the word line in a memory cell array; and higher level bit signals are input into a Y decoder for selecting the Y switch control signal lines. The addresses in the memory cell array are arranged sequentially in the direction of the data lines.Type: GrantFiled: May 26, 2000Date of Patent: August 28, 2001Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.Inventors: Kohei Sakurai, Tatsumi Yamauchi, Masahiro Matsumoto, Fumio Murabayashi, Hiromichi Yamada, Atsushi Miyazaki, Keiji Hanzawa