Patents by Inventor Fumio Ohtake
Fumio Ohtake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7856892Abstract: A measurable flow-rate range is increased to enhance usability. A flow-rate measuring method for measuring the flow rate of a fluid inside a tube is provided. This method uses a thermal-marker generator that heats the fluid flowing through the tube from the outside thereof to generate a thermal marker in the fluid inside the tube and a thermal-marker detector disposed downstream of the thermal-marker generator and configured to detect the thermal marker in the fluid inside the tube generated by the thermal-marker generator, so as to measure the flow rate on the basis of the distance between the thermal-marker generator and the thermal-marker detector, a time period between a point at which the thermal marker in the fluid inside the tube is generated by the thermal-marker generator and a point at which the thermal marker is detected by the thermal-marker detector, and the cross-sectional area of the tube.Type: GrantFiled: January 30, 2009Date of Patent: December 28, 2010Assignee: Surpass Industry Co, Ltd.Inventor: Fumio Ohtake
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Publication number: 20090205441Abstract: A measurable flow-rate range is increased to enhance usability. A flow-rate measuring method for measuring the flow rate of a fluid inside a tube is provided. This method uses a thermal-marker generator that heats the fluid flowing through the tube from the outside thereof to generate a thermal marker in the fluid inside the tube and a thermal-marker detector disposed downstream of the thermal-marker generator and configured to detect the thermal marker in the fluid inside the tube generated by the thermal-marker generator, so as to measure the flow rate on the basis of the distance between the thermal-marker generator and the thermal-marker detector, a time period between a point at which the thermal marker in the fluid inside the tube is generated by the thermal-marker generator and a point at which the thermal marker is detected by the thermal-marker detector, and the cross-sectional area of the tube.Type: ApplicationFiled: January 30, 2009Publication date: August 20, 2009Applicant: Surpass Industry Co., Ltd.Inventor: Fumio Ohtake
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Patent number: 7315062Abstract: A semiconductor device includes: a semiconductor substrate having a source region and a drain region; and an offset region that is provided in the semiconductor substrate and extends from an edge of a gate electrode toward the drain region. The offset region includes multiple regions having different impurity concentrations formed by an ion implantation with a mask having an opening ratio that changes from the gate electrode to the drain region and by subsequent thermal treatment. The multiple regions include a concentration gradient region that is interposed between adjacent ones of the multiple regions and has the impurity concentration that gradually changes.Type: GrantFiled: March 30, 2005Date of Patent: January 1, 2008Assignee: Eudyna Devices Inc.Inventor: Fumio Ohtake
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Publication number: 20060220124Abstract: A semiconductor device includes a gate electrode, a source electrode, a drain electrode and an electrode part. The gate electrode is formed above a semiconductor layer. The source electrode and the drain electrode are formed on the semiconductor layer. The gate electrode is located between the source electrode and the drain electrode. The electrode part is provided between the gate electrode and the drain electrode and has a width of 10 nm to 300 nm in a direction between the gate electrode and the drain electrode.Type: ApplicationFiled: March 30, 2006Publication date: October 5, 2006Applicant: EUDYNA DEVICES, INC.Inventor: Fumio Ohtake
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Publication number: 20050230765Abstract: A semiconductor device includes: a semiconductor substrate having a source region and a drain region; and an offset region that is provided in the semiconductor substrate and extends from an edge of a gate electrode toward the drain region. The offset region includes multiple regions having different impurity concentrations formed by an ion implantation with a mask having an opening ratio that changes from the gate electrode to the drain region and by subsequent thermal treatment. The multiple regions include a concentration gradient region that is interposed between adjacent ones of the multiple regions and has the impurity concentration that gradually changes.Type: ApplicationFiled: March 30, 2005Publication date: October 20, 2005Applicant: EUDYNA DEVICES INC.Inventor: Fumio Ohtake
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Patent number: 6939787Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: GrantFiled: October 13, 2004Date of Patent: September 6, 2005Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20050062115Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: ApplicationFiled: October 13, 2004Publication date: March 24, 2005Applicants: FUJITSU LIMITED, KABUSHIKI KAISHA TOSHIBAInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20050047704Abstract: An optical semiconductor device that includes: an optical waveguide formed on a substrate; a modulation electrode and a conductive region that form a modulation region in the optical waveguide; and an interconnection pattern electrically connected to the modulation electrode. In this optical semiconductor device, the conductive region is formed in an area that excludes a region in which the interconnection pattern overlaps the optical waveguide.Type: ApplicationFiled: August 24, 2004Publication date: March 3, 2005Applicant: EUDYNA DEVICES INC.Inventor: Fumio Ohtake
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Publication number: 20020056874Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: ApplicationFiled: December 28, 2000Publication date: May 16, 2002Inventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Patent number: 5271197Abstract: The present invention provides an earthquake resistant multi-story building which is characterized by having an energy concentration story. The energy concentration story has an elasto-plastic force-displacement relationship regarding horizontal force and displacement. The force-displacement relationship is characterized in that: (a) stiffness in elastic range (F.sub.y /d.sub.y) is generally equal to an optimal stiffness of the same story according to an elastic design concept; (b) the yield strength F.sub.y is generally less than 80% of an optimum yield strength; (c) stiffness in plastic range is positive and generally less than about a half of the stiffness in the elastic range; and (d) ultimate displacement is generally at least twice as large as the yield displacement.Type: GrantFiled: August 13, 1992Date of Patent: December 21, 1993Assignees: Shimizu Construction Co., Ltd., Sumitomo Metal Industries, Ltd.Inventors: Toshio Uno, Yoshitaka Yabe, Kiyoshi Ikura, Shinji Mase, Toshihiko Hirama, Hideo Shimizu, Masahiro Kato, Fumio Ohtake, Takehiko Terada, Tomomi Kanemitsu
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Patent number: 5110371Abstract: An aluminum alloy consists of, by weight, from 0.08 to 0.50 percent silicon, from 0.15 to 0.90 percent iron, the weight ratio of iron to silicon being from 1.4 to 2.2, and the remainder aluminum, intermetallic compounds of .alpha.-type Al-Fe-Si system being contained in the alloy. A light gray oxide film is formed on the alloy by anodic treatment.Type: GrantFiled: July 9, 1991Date of Patent: May 5, 1992Assignee: Nippon Light Metal Company, Ltd.Inventors: Takeshi Moriyama, Katsuji Ogawa, Fumio Ohtake, Akito Nishizawa
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Patent number: 4597278Abstract: An I-beam is made lighter in weight by corrugating the central portion of its web. Dimension of the corrugating is determined by predetermined experimental equations. The corrugating work is performed by a pair of complementary intermeshing rolls having the same dimensions.Type: GrantFiled: July 3, 1985Date of Patent: July 1, 1986Assignee: Sumitomo Metal Industries, Ltd.Inventors: Masami Hamada, Kiyokazu Tanaka, Takeshi Kikuchi, Yasuhiro Asai, Chihiro Hayashi, Fumio Ohtake