Abstract: A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current MOSFET has a drain and a gate common with discharge control MOSFET. The charge current detection resistances and the discharge current detection resistance are provided in correspondence to the charge current detection MOSFET and the discharge current detection MOSFET, respectively.

Abstract: A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.

Abstract: A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current detection MOSFET has a drain and a gate common with the discharge control MOSFET. The resistancesare provided in correspondence to the charge and discharge current detection MOSFETs. The control circuit generates a gate control signal for the charge control and current detection MOSFETs by using one of the resistances and generates a gate control signal for the discharge control and current detection MOSFETs 20 by using another one of the resistances.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A power supply circuit of the present invention includes a voltage boosting capacitor, a first switch, a second switch, an addition comparison circuit, and a control circuit. The first switch charges the voltage boosting capacitor by applying a first voltage thereto. The second switch connects a second voltage serially to the voltage boosting capacitor that is already charged, thereby boosting the voltage therein. The addition comparison circuit adds up the voltage of the voltage boosting capacitor and the second voltage and compares the comparison result, with a predetermined threshold value. The control circuit controls the on/off state of the first switch according to the comparison result of the addition comparison circuit.

Abstract: A voltage regulator circuit includes a differential amplifier circuit that includes a first input terminal and a second input terminal, the first input terminal supplied a reference voltage, an output circuit that receives an output voltage from the differential amplifier circuit to generate a first voltage based on the output voltage, and a control circuit that compares the first voltage with a second voltage, and outputs the first voltage or a third voltage to the second input terminal based on a result of comparing, the second and third voltage being different from the first voltage.

Abstract: It is desired for semiconductor devices to reduce an inrush current and an overshoot. According to the voltage regulator circuit of the present invention, when a power supply is turned on, a switch SW1 is turned on in response to a control signal CTR1, a switch SW2 is turned off, and a reference voltage Vref is input to the first (+IN) and second (?IN) inputs of a differential amplifier AMP1 as a common voltage. When a common voltage is supplied to the first (+IN) and second (?IN) inputs, the current I flows into a smoothing capacitor C1 from the high-voltage power supply (VDD) via the differential amplifier AMP1 is regulated to be small. Namely, an inrush current can be reduced. Further, according to the voltage regulator circuit 30 of the present invention, the increase of the output voltage Vout from the differential amplifier AMP1 is relaxed so that the overshoot can be suppressed.

Abstract: Provided is a drive circuit including a PDAC and an NDAC that respectively select a positive gray scale voltage and a negative gray scale voltage according to gray scale data, a positive Amp and a negative Amp, an output selection switch that inverts outputs of the positive Amp and the negative Amp, an output switch that makes switching to disconnect an amplifier output from data lines during a switching period, a charge share switch that short-circuits the data lines during the switching period, and data selector circuits that set an amplifier input to a fixed voltage not dependent on a gray scale voltage corresponding to gray scale data for display during the switching period.

Abstract: A driving circuit, which drives a display panel in a voltage range between a high negative voltage and a high positive voltage, includes: an electric charge discharging circuit; and a test external terminal. The electric charge discharging circuit connects a first terminal supplied with the high negative voltage to a second terminal of a ground voltage in response to a drop of a power source voltage. The test external terminal is connected to the electric charge discharging circuit. The high negative voltage is supplied to the semiconductor substrate. The electric charge discharging circuit interrupts a connection between the first terminal and the second terminal based on a control signal from the test external terminal.

Abstract: A power supply circuit in accordance with the invention includes a charge-pump circuit and a control circuit. The charge-pump circuit includes first and second capacitors. The control circuit controls the charging voltage of the first and second capacitors. In this way, the power supply circuit outputs a constant output voltage based on the charging voltages of the first and second capacitors.

Abstract: A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage.

Abstract: It is desired for semiconductor devices to reduce an inrush current and an overshoot. According to the voltage regulator circuit of the present invention, when a power supply is turned on, a switch SW1 is turned on in response to a control signal CTR1, a switch SW2 is turned off, and a reference voltage Vref is input to the first (+IN) and second (?IN) inputs of a differential amplifier AMP1 as a common voltage. When a common voltage is supplied to the first (+IN) and second (?IN) inputs, the current I flows into a smoothing capacitor C1 from the high-voltage power supply (VDD) via the differential amplifier AMP1 is regulated to be small. Namely, an inrush current can be reduced. Further, according to the voltage regulator circuit 30 of the present invention, the increase of the output voltage Vout from the differential amplifier AMP1 is relaxed so that the overshoot can be suppressed.

Abstract: A source driver circuit includes a bias circuit supplying a bias current corresponding to a control signal, and a source amplifier circuit supplying a voltage corresponding to the bias current to a pixel element in a display panel. The source driver circuit further includes a controller circuit generating the control signal according to the frequency of a vertical synchronizing signal for the display panel.

Abstract: A driving circuit, which drives a display panel in a voltage range between a high negative voltage and a high positive voltage, includes: an electric charge discharging circuit; and a test external terminal. The electric charge discharging circuit connects a first terminal supplied with the high negative voltage to a second terminal of a ground voltage in response to a drop of a power source voltage. The test external terminal is connected to the electric charge discharging circuit. The high negative voltage is supplied to the semiconductor substrate. The electric charge discharging circuit interrupts a connection between the first terminal and the second terminal based on a control signal from the test external terminal.

Abstract: A power supply circuit of the present invention includes a voltage boosting capacitor, a first switch, a second switch, an addition comparison circuit, and a control circuit. The first switch charges the voltage boosting capacitor by applying a first voltage thereto. The second switch connects a second voltage serially to the voltage boosting capacitor that is already charged, thereby boosting the voltage therein. The addition comparison circuit adds up the voltage of the voltage boosting capacitor and the second voltage and compares the comparison result, with a predetermined threshold value. The control circuit controls the on/off state of the first switch according to the comparison result of the addition comparison circuit.

Abstract: A satellite channel interface (SCI) is constituted by an analog section having a multiplexer unit and a down converter unit, and a digital section constituted by a modulator-demodulator unit. The satellite channel interface has a single printed circuit board on which all of the above units are formed. A rectangular member surrounds the analog section, and a shield cover shields an opening portion of the rectangular member. The single printed circuit board is a multi-layered board constituted by at least three conductive layers, of which the bottom two layers are grounding electrodes. The SCI does not require the terminals and cables which are otherwise necessary, can be made compact, and can be manufactured with the reduced number of processing steps.