Patents by Inventor Fumitaka Izuhara

Fumitaka Izuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8884792
    Abstract: Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Patent number: 8442333
    Abstract: The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata, Fumitaka Izuhara, Motoki Kimura
  • Publication number: 20120263233
    Abstract: The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 18, 2012
    Inventors: Kenichi IWATA, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
  • Patent number: 8264386
    Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Patent number: 8223838
    Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
  • Publication number: 20110080308
    Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
    Type: Application
    Filed: December 6, 2010
    Publication date: April 7, 2011
    Inventors: Hiroaki NAKATA, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Patent number: 7876829
    Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shohei Saito, Masaru Hase, Fumitaka Izuhara, Seiji Mochizuki
  • Patent number: 7864082
    Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Publication number: 20090304078
    Abstract: The variable length decoder has a memory device including a plurality of lookup tables, and sequentially decodes codewords of variable-length codes using the memory device. The decoded values corresponding to the codewords and control information pieces are stored in the lookup tables. In decoding one codeword, one lookup table is selected from among the plurality of lookup tables. In the decode, one decoded value corresponding to the one codeword, and a control information piece for selecting a next lookup table depending on the decoded value and used for a next decode are produced from the selected lookup table in response to the one codeword in parallel.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 10, 2009
    Inventors: Takafumi YUASA, Hiroaki NAKATA, Fumitaka IZUHARA, Kazushi AKIE, Motoki KIMURA
  • Publication number: 20090245664
    Abstract: The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves.
    Type: Application
    Filed: March 10, 2009
    Publication date: October 1, 2009
    Inventors: Keisuke MATSUMOTO, Seiji MOCHIZUKI, Kenichi IWATA, Fumitaka IZUHARA, Motoki KIMURA
  • Publication number: 20090237278
    Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 24, 2009
    Inventors: Hiroaki NAKATA, Fumitaka IZUHARA, Kazushi AKIE, Takafumi YUASA
  • Publication number: 20090144527
    Abstract: The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control stream. Double buffer areas are prepared in a memory of the stream processing apparatus into which the program and the parameter are stored. The location of the data stream to be input is written in the control stream, and buffers for reading the data stream are multiplexed so as to read in advance the top portion of the data stream to be processed next.
    Type: Application
    Filed: November 28, 2008
    Publication date: June 4, 2009
    Inventors: Hiroaki NAKATA, Takafumi YUASA, Fumitaka IZUHARA, Kazushi AKIE, Motoki KIMURA
  • Patent number: 7535386
    Abstract: A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Publication number: 20080294878
    Abstract: When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.
    Type: Application
    Filed: April 11, 2008
    Publication date: November 27, 2008
    Inventors: Takafumi YUASA, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Fumitaka Izuhara, Kazushi Akie
  • Publication number: 20080212683
    Abstract: An image decoding device according to the present invention is an image decoding device responding to decoding of an image encoding method selecting an encoding table and an encoding format to use according to the kind of a parameter included in encoded data and comprises a bit stream processing unit converting a bit stream of the encoded data into an intermediate format and an image processing unit decoding data converted into the intermediate format and converting the same into image data. The bit stream processing unit and the image processing unit start independently. An image encoding device according to the present invention, in the same manner, comprises an image processing unit converting image data to be encoded into an intermediate format and a bit stream processing unit encoding the data converted into the intermediate format and converting the same into a bit stream. Thereby, image encoding and decoding processings with a low operation frequency and low power consumption is realized.
    Type: Application
    Filed: November 14, 2007
    Publication date: September 4, 2008
    Inventors: Hiroaki Nakata, Takafumi Yuasa, Fumitaka Izuhara, Kazushi Akie
  • Publication number: 20080068235
    Abstract: A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 20, 2008
    Inventors: HIROAKI NAKATA, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
  • Publication number: 20080031329
    Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 7, 2008
    Inventors: Kenichi IWATA, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
  • Publication number: 20060126741
    Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.
    Type: Application
    Filed: November 25, 2005
    Publication date: June 15, 2006
    Inventors: Shohei Saito, Masaru Hase, Fumitaka Izuhara, Seiji Mochizuki