Patents by Inventor Fumitaka Izuhara
Fumitaka Izuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8884792Abstract: Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.Type: GrantFiled: September 4, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Patent number: 8442333Abstract: The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves.Type: GrantFiled: March 10, 2009Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata, Fumitaka Izuhara, Motoki Kimura
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Publication number: 20120263233Abstract: The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Inventors: Kenichi IWATA, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
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Patent number: 8264386Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: GrantFiled: December 6, 2010Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Patent number: 8223838Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.Type: GrantFiled: August 6, 2007Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Kenichi Iwata, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
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Publication number: 20110080308Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: ApplicationFiled: December 6, 2010Publication date: April 7, 2011Inventors: Hiroaki NAKATA, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Patent number: 7876829Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.Type: GrantFiled: November 25, 2005Date of Patent: January 25, 2011Assignee: Renesas Electronics CorporationInventors: Shohei Saito, Masaru Hase, Fumitaka Izuhara, Seiji Mochizuki
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Patent number: 7864082Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: GrantFiled: May 18, 2009Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20090304078Abstract: The variable length decoder has a memory device including a plurality of lookup tables, and sequentially decodes codewords of variable-length codes using the memory device. The decoded values corresponding to the codewords and control information pieces are stored in the lookup tables. In decoding one codeword, one lookup table is selected from among the plurality of lookup tables. In the decode, one decoded value corresponding to the one codeword, and a control information piece for selecting a next lookup table depending on the decoded value and used for a next decode are produced from the selected lookup table in response to the one codeword in parallel.Type: ApplicationFiled: May 28, 2009Publication date: December 10, 2009Inventors: Takafumi YUASA, Hiroaki NAKATA, Fumitaka IZUHARA, Kazushi AKIE, Motoki KIMURA
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Publication number: 20090245664Abstract: The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves.Type: ApplicationFiled: March 10, 2009Publication date: October 1, 2009Inventors: Keisuke MATSUMOTO, Seiji MOCHIZUKI, Kenichi IWATA, Fumitaka IZUHARA, Motoki KIMURA
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Publication number: 20090237278Abstract: A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.Type: ApplicationFiled: May 18, 2009Publication date: September 24, 2009Inventors: Hiroaki NAKATA, Fumitaka IZUHARA, Kazushi AKIE, Takafumi YUASA
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Publication number: 20090144527Abstract: The present invention provides a stream processing apparatus capable of improving the processing performance in the case of continuously processing a plurality of data streams. A control stream, different from a data stream, is prepared, and a program and a parameter are updated in advance in accordance with the control stream. Double buffer areas are prepared in a memory of the stream processing apparatus into which the program and the parameter are stored. The location of the data stream to be input is written in the control stream, and buffers for reading the data stream are multiplexed so as to read in advance the top portion of the data stream to be processed next.Type: ApplicationFiled: November 28, 2008Publication date: June 4, 2009Inventors: Hiroaki NAKATA, Takafumi YUASA, Fumitaka IZUHARA, Kazushi AKIE, Motoki KIMURA
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Patent number: 7535386Abstract: A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.Type: GrantFiled: August 28, 2007Date of Patent: May 19, 2009Assignee: Renesas Technology Corp.Inventors: Hiroaki Nakata, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20080294878Abstract: When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.Type: ApplicationFiled: April 11, 2008Publication date: November 27, 2008Inventors: Takafumi YUASA, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Fumitaka Izuhara, Kazushi Akie
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Publication number: 20080212683Abstract: An image decoding device according to the present invention is an image decoding device responding to decoding of an image encoding method selecting an encoding table and an encoding format to use according to the kind of a parameter included in encoded data and comprises a bit stream processing unit converting a bit stream of the encoded data into an intermediate format and an image processing unit decoding data converted into the intermediate format and converting the same into image data. The bit stream processing unit and the image processing unit start independently. An image encoding device according to the present invention, in the same manner, comprises an image processing unit converting image data to be encoded into an intermediate format and a bit stream processing unit encoding the data converted into the intermediate format and converting the same into a bit stream. Thereby, image encoding and decoding processings with a low operation frequency and low power consumption is realized.Type: ApplicationFiled: November 14, 2007Publication date: September 4, 2008Inventors: Hiroaki Nakata, Takafumi Yuasa, Fumitaka Izuhara, Kazushi Akie
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Publication number: 20080068235Abstract: A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.Type: ApplicationFiled: August 28, 2007Publication date: March 20, 2008Inventors: HIROAKI NAKATA, Fumitaka Izuhara, Kazushi Akie, Takafumi Yuasa
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Publication number: 20080031329Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.Type: ApplicationFiled: August 6, 2007Publication date: February 7, 2008Inventors: Kenichi IWATA, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
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Publication number: 20060126741Abstract: The present invention provides a technology that is implemented in a motion compensation image coding device or a coding method and intended to code motion picture data in real time by performing a decreased number of arithmetic operations so as to determine a motion vector. In motion compensation image coding, macroblocks and sub-blocks into which each of the macroblocks is divided are searched for a motion vector with integer pixel precision. Based on the results of the search, a shape of a block that should be searched for a motion vector with decimal pixel precision is determined as a shape mode. The block of the shape mode is searched for a motion vector with decimal pixel precision, whereby a motion vector needed to produce predictive image data is determined.Type: ApplicationFiled: November 25, 2005Publication date: June 15, 2006Inventors: Shohei Saito, Masaru Hase, Fumitaka Izuhara, Seiji Mochizuki