Patents by Inventor Fumitaka Sato
Fumitaka Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7863167Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.Type: GrantFiled: February 13, 2009Date of Patent: January 4, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata
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Patent number: 7858502Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: GrantFiled: August 13, 2009Date of Patent: December 28, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 7843040Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate (1), such as a (0001)-cut sapphire substrate, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus (11). Next, gaseous iron compound GFe from a source (13) for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source (15) are caused to react with each other in a mixing container (16) to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source (17), and second substance gas GGa containing elemental gallium are supplied to a reaction tube (21) to form iron-doped gallium nitride (23) on the substrate (1).Type: GrantFiled: December 2, 2008Date of Patent: November 30, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Akinori Koukitu, Yoshinao Kumagai, Yoshiki Miura, Kikurou Takemoto, Fumitaka Sato
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Publication number: 20100280749Abstract: An on-vehicle guidance apparatus is characterized in including an output sound control means for acquiring a sound volume setting of onboard equipment, a sound volume determining means for determining whether or not the sound volume setting is smaller than a predetermined threshold, and a guidance output control means for issuing a command for carrying out voice guidance in response to a determination signal from the sound volume determining means at a time when the sound volume setting becomes smaller than the above-mentioned threshold.Type: ApplicationFiled: November 19, 2008Publication date: November 4, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuki Furumoto, Tadashi Suzuki, Fumitaka Sato
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Publication number: 20100275836Abstract: The present method for growing group III nitride crystal includes the steps of: preparing a substrate including group III nitride seed crystal constituting one main surface thereof; forming a plurality of facets on the main surface of the substrate through vapor phase etching; and growing group III nitride crystal on the main surface on which the facets are formed. In this way, group III nitride crystal having a low dislocation density can be obtained readily and efficiently.Type: ApplicationFiled: January 8, 2009Publication date: November 4, 2010Applicant: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata
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Patent number: 7822613Abstract: In a vehicle-mounted control apparatus, a control unit 2 displays guidance on an operation of the vehicle-mounted control apparatus by voice input on a display device 6, and makes the user get training so that the user can master the techniques for operating the vehicle-mounted control apparatus (in step ST4). At this time, by using a voice which the user tries to input in order to master the techniques for operating the vehicle-mounted control apparatus, the voice recognition unit 5 learns the features of the user's voice in the background, and computes recognition parameters. Thereby, the user can know how to operate the vehicle-mounted control apparatus and can also register the features of the voice in the vehicle-mounted control apparatus.Type: GrantFiled: October 7, 2003Date of Patent: October 26, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsutomu Matsubara, Masato Hirai, Emiko Kido, Fumitaka Sato
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Patent number: 7772585Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: June 6, 2006Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7771532Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: February 19, 2009Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7723142Abstract: A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater than that of the GaN crystal, and growing the GaN crystal to a thickness of at least 1 mm on the GaN seed crystal substrate. Accordingly, there can be provided a method of producing a GaN crystal that can suppress generation of a crack and grow a thick GaN crystal, and a GaN crystal substrate.Type: GrantFiled: May 30, 2008Date of Patent: May 25, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naoki Matsumoto, Fumitaka Sato, Seiji Nakahata, Takuji Okahisa, Koji Uematsu
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Publication number: 20100106407Abstract: A navigation system has: a candidate input device 14 for inputting a search key; an input vocabulary storage 11 that stores words to become candidates of a search key input from the candidate input device; a vehicle information storage 12 for storing vehicle information relating to a vehicle; a preference information storage 13 for storing preference information representing user' preference in connection with the words stored in the input vocabulary storage; an input word estimating module 17 for searching the input vocabulary storage for words corresponding to the search key input from the candidate input device, and for estimating the words obtained by the search in accordance with an order of priority based on the vehicle information read out of the vehicle condition storage and the preference information read out of the preference information storage; and a candidate output device 15 for outputting the words delivered from the input word estimating module as candidates.Type: ApplicationFiled: April 17, 2008Publication date: April 29, 2010Inventors: Wataru Yamazaki, Fumitaka Sato, Atsushi Kohno, Yuta Kawana, Osamu Gojo
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Publication number: 20100009526Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: ApplicationFiled: August 13, 2009Publication date: January 14, 2010Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi KASAI, Takuji OKAHISA, Shunsuke FUJITA, Naoki MATSUMOTO, Hideyuki IJIRI, Fumitaka SATO, Kensaku MOTOKI, Seiji NAKAHATA, Koji UEMATSU, Ryu HIROTA
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Publication number: 20090289261Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).Type: ApplicationFiled: June 3, 2009Publication date: November 26, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Fumitaka SATO, Seiji Nakahata
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Patent number: 7589000Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: GrantFiled: December 22, 2006Date of Patent: September 15, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20090209091Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.Type: ApplicationFiled: February 13, 2009Publication date: August 20, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Fumitaka Sato, Seiji Nakahata
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Patent number: 7556687Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).Type: GrantFiled: November 22, 2006Date of Patent: July 7, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata
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Publication number: 20090155989Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts not burying the facets, maintaining the convex facet hills on ? and the network concavities on excluding dislocations in the facet hills down to the outlining concavities on forming a defect accumulating region H on decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: ApplicationFiled: February 19, 2009Publication date: June 18, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji UEMATSU, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7533278Abstract: According to one embodiment, an EC/KBC reads data of an acceleration sensor. The EC/KBC determines whether a computer is in a top heat state. If the EC/KBC determines that the computer is in the top heat state, it notifies a BIOS stored in a BIOS-ROM of a message to this effect. The BIOS which is notified from the EC/KBC that the computer is in the top heat state notifies an OS (Operating System) of the message to this effect. The OS sets a CPU to a power saving mode by an existing means such as the power saving utility of the OS, and sets the computer to the power saving mode.Type: GrantFiled: January 27, 2006Date of Patent: May 12, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Shogo Maeshima, Fumitaka Sato
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Publication number: 20090108297Abstract: A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 ?m to 100 ?m are arranged at an interval Dw from 250 ?m to 2000 ?m, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R5/3 is set to 1 to 10 and a gas containing iron, and removing the underlying substrate, to thereby obtain a free-standing semi-insulating nitride semiconductor substrate having a specific resistance not smaller than 1×105 ?cm and a thickness not smaller than 100 ?m. Thus, the semi-insulating nitride semiconductor crystal substrate in which warpage is less and cracking is less likely can be obtained.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka SATO, Seiji NAKAHATA, Makoto KIYAMA
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Patent number: 7518216Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate 1, such as a sapphire substrate having the (0001) plane, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus 11. Next, gaseous iron compound GFe from a source 13 for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source 15 are caused to react with each other in a mixing container 16 to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source 17, and second substance gas GGa containing elemental gallium are supplied to a reaction tube 21 to form iron-doped gallium nitride 23 on the substrate 1.Type: GrantFiled: March 20, 2006Date of Patent: April 14, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Akinori Koukitu, Yoshinao Kumagai, Yoshiki Miura, Kikurou Takemoto, Fumitaka Sato
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Publication number: 20090079036Abstract: A method of forming an iron-doped gallium nitride for a semi-insulating GaN substrate is provided. A substrate (1), such as a (0001)-cut sapphire substrate, is placed on a susceptor of a metalorganic hydrogen chloride vapor phase apparatus (11). Next, gaseous iron compound GFe from a source (13) for an iron compound, such as ferrocene, and hydrogen chloride gas G1HCl from a hydrogen chloride source (15) are caused to react with each other in a mixing container (16) to generate gas GFeComp of an iron-containing reaction product, such as iron chloride (FeCl2). In association with the generation, the iron-containing reaction product GFeComp, first substance gas GN containing elemental nitrogen from a nitrogen source (17), and second substance gas GGa containing elemental gallium are supplied to a reaction tube (21) to form iron-doped gallium nitride (23) on the substrate (1).Type: ApplicationFiled: December 2, 2008Publication date: March 26, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Akinori Koukitu, Yoshinao Kumagai, Yoshiki Miura, Kikurou Takemoto, Fumitaka Sato