Patents by Inventor Fumito Itou
Fumito Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9545026Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip protrudes more along a normal to the first surface than ends of the external terminals do.Type: GrantFiled: February 2, 2015Date of Patent: January 10, 2017Assignee: PANASONIC CORPORATIONInventors: Toshiyuki Fukuda, Keisuke Kodera, Fumito Itou, Toshihiro Miyoshi
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Publication number: 20160322342Abstract: A semiconductor device includes a substrate made of metal, a first metal wiring disposed above the substrate, a first semiconductor element and a second semiconductor element disposed above the first metal wiring, and a second metal wiring disposed above the first semiconductor element and the second semiconductor element. Furthermore, the semiconductor device includes a plurality of projections disposed in at least one of a space between each of the first semiconductor element and the second semiconductor element, and the first metal wiring, and a space between each of the first semiconductor element and the second semiconductor element, and the second metal wiring.Type: ApplicationFiled: January 7, 2015Publication date: November 3, 2016Applicant: Panasonic Intellectual Property Management Co. LtInventors: JUNICHI KIMURA, MASAHISA NAKAGUCHI, FUMITO ITOU, NORIMITSU HOZUMI
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Patent number: 9474179Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: GrantFiled: August 7, 2015Date of Patent: October 18, 2016Assignee: PANASONIC CORPORATIONInventors: Yukitoshi Ota, Fumito Itou, Kiyomi Hagihara
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Publication number: 20150359119Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: ApplicationFiled: August 7, 2015Publication date: December 10, 2015Inventors: YUKITOSHI OTA, FUMITO ITOU, KIYOMI HAGIHARA
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Publication number: 20150181739Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip more protrudes along a normal to the first surface than ends of the external terminals do.Type: ApplicationFiled: February 2, 2015Publication date: June 25, 2015Inventors: Toshiyuki FUKUDA, Keisuke KODERA, Fumito ITOU, Toshihiro MIYOSHI
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Patent number: 8421233Abstract: A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion.Type: GrantFiled: April 2, 2010Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventors: Chikako Chida, Fumito Itou, Hiroshige Hirano
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Publication number: 20120256322Abstract: A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Applicant: PANASONIC CORPORATIONInventors: Fumito Itou, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20100289151Abstract: A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion.Type: ApplicationFiled: April 2, 2010Publication date: November 18, 2010Inventors: Chikako CHIDA, Fumito Itou, Hiroshige Hirano
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Patent number: 7521288Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: GrantFiled: March 14, 2007Date of Patent: April 21, 2009Assignee: Panasonic CorporationInventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Patent number: 7498668Abstract: A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.Type: GrantFiled: June 27, 2006Date of Patent: March 3, 2009Assignee: Panasonic CorporationInventors: Takeshi Kawabata, Fumito Itou
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Patent number: 7298045Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.Type: GrantFiled: November 24, 2004Date of Patent: November 20, 2007Assignee: Matsushita Electric Industrial Co., LtdInventors: Hisaki Fujitani, Fumito Itou, Toshitaka Akahoshi, Toshiyuki Fukuda
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Publication number: 20070187811Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: ApplicationFiled: March 14, 2007Publication date: August 16, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Patent number: 7239021Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: GrantFiled: June 30, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Publication number: 20070096291Abstract: A lower module of a stacked semiconductor device includes a first substrate and a first semiconductor chip held above the first substrate. The top surface of the first substrate is provided with a plurality of first chip connection terminals electrically connected to the first chip terminals, respectively, and a plurality of upper module connection terminals electrically connectable to an upper module provided with a second semiconductor chip. The back surface of the first substrate is provided with a plurality of external substrate connection terminals. Each of the first chip connection terminals is electrically connected to a corresponding one of the external substrate connection terminals, and each of the upper module connection terminals is electrically connected between a corresponding one of the chip connection terminals and a corresponding one of the external substrate connection terminals.Type: ApplicationFiled: June 27, 2006Publication date: May 3, 2007Inventors: Takeshi Kawabata, Fumito Itou
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Patent number: 7138706Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.Type: GrantFiled: June 24, 2003Date of Patent: November 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Kouichi Yamauchi, Yasutake Yaguchi
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Publication number: 20060091563Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.Type: ApplicationFiled: November 21, 2005Publication date: May 4, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi
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Patent number: 6992396Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.Type: GrantFiled: August 28, 2003Date of Patent: January 31, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi
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Publication number: 20050116353Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.Type: ApplicationFiled: November 24, 2004Publication date: June 2, 2005Applicant: Matsushita Elec. Ind. Co. Ltd.Inventors: Hisaki Fujitani, Fumito Itou, Toshitaka Akahoshi, Toshiyuki Fukuda
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Publication number: 20050003580Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: ApplicationFiled: June 30, 2004Publication date: January 6, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Publication number: 20040126926Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.Type: ApplicationFiled: August 28, 2003Publication date: July 1, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi