Abstract: A MISFET having a buried gate is formed by forming a dummy gate electrode on a semiconductor substrate, forming source/drain regions with the dummy electrode as a mask, after forming an insulating film in a way to bury the dummy gate electrode, while exposing an upper surface of the dummy gate, removing the dummy gate electrode and forming a first trench in the insulating film, enlarging the width of the first trench to provide a second trench in the insulating film which is wider than the first trench, forming a gate insulating film along the inner surface of the second trench, and forming a gate electrode in the second trench with the gate insulating film intervening therebetween. By doing so it is possible to control an offset between the end of the gate electrode and the ends of source/drain diffusion layers and a MISFET thus obtained operates stably.

Abstract: A semiconductor device where an interface circuit operating on a high power supply voltage and exchanging signals and data with an external device and an internal circuit operating on a low power supply voltage are integrated in a single chip. The interface circuit includes a transistor whose gate insulating film is made of SiO2. The internal circuit includes a transistor whose gate insulating film is made of an oxynitride film of nitrogen-added SiO2. Boron or BF2 has been introduced into the gate electrodes of the p-channel transistors among those whose gate insulating films have been made of an oxynitride film.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and drain regions of the MOS transistor, impurity ions are implanted using the first and second side walls provided to the gate electrode as a mask, and then the heat treatment for impurity activation is performed after removing the second side wall near the source and drain regions doped with high-concentration impurity ions. By removing the second side wall prior to the heat treatment, the stress applied to the edges of the high-concentration impurity doped regions in an amorphous state is decreased. The defects therefore can be suppressed from being formed at the edges of the source and drain regions near the gate electrode in the recrystallization of the amorphous layer by the heat treatment.

Abstract: In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.

Abstract: A semiconductor device where an interface circuit operating on a high power supply voltage and exchanging signals and data with an external device and an internal circuit operating on a low power supply voltage are integrated in a single chip. The interface circuit includes a transistor whose gate insulating film is made of SiO2. The internal circuit includes a transistor whose gate insulating film is made of an oxynitride film of nitrogen-added SiO2. Boron or BF2 has been introduced into the gate electrodes of the p-channel transistors among those whose gate insulating films have been made of an oxynitride film.

Abstract: In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.

Abstract: A semiconductor device where an interface circuit operating on a high power supply voltage and exchanging signals and data with an external device and an internal circuit operating on a low power supply voltage are integrated in a single chip. The interface circuit includes a transistor whose gate insulating film is made of SiO2. The internal circuit includes a transistor whose gate insulating film is made of an oxynitride film of nitrogen-added SiO2. Boron or BF2 has been introduced into the gate electrodes of the p-channel transistors among those whose gate insulating films have been made of an oxynitride film.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench for isolating an element region on a semiconductor substrate, burying a first oxide film in the trench so as to contact a surface of the trench, flattening a surface of the first oxide film, heating the semiconductor substrate to form a second oxide film at an interface between the surface of the trench and the first oxide film, and annealing the semiconductor substrate.

Abstract: A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and drain regions of the MOS transistor, impurity ions are implanted using the first and second side walls provided to the gate electrode as a mask, and then the heat treatment for impurity activation is performed after removing the second side wall near the source and drain regions doped with high-concentration impurity ions. By removing the second side wall prior to the heat treatment, the stress applied to the edges of the high-concentration impurity doped regions in an amorphous state is decreased. The defects therefore can be suppressed from being formed at the edges of the source and drain regions near the gate electrode in the recrystallization of the amorphous layer by the heat treatment.

Abstract: A polycrystalline silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the polycrystalline silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polycide gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten silicide layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten silicide layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten silicide layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.

Abstract: MOSFET having a fine gate structure comprises a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed in the semiconductor substrate to define a channel region therebetween, a first insulating film provided over the source region, a second insulating film formed over the first insulating film to provide a side wall, a gate insulating film provided on the semiconductor substrate to cover the channel region, and a gate electrode provided over the gate insulating film to extend to the second insulating film and to cover the side wall. In the structure, the gate electrode is provided to have a thickness for defining an effective channel length at the side wall of the second insulating film.

Abstract: A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate.

Abstract: An amorphous silicon layer is formed on the side wall of a first wiring layer having a predetermined wiring width and formed in a predetermined shape by patterning. A silicon oxide layer is covering the first wiring layer and the amorphous silicon layer, and a through-hole is formed in the silicon oxide layer so that a portion of the first wiring layer is exposed. A tungsten layer is filling the through-hole, and a second wiring layer connected to the tungsten layer is formed on the silicon oxide layer.

Abstract: A poly-crystal silicon layer is formed on an N-type silicon substrate via an oxide film. A contact hole is formed on the poly-crystal silicon layer by applying a photoresist mask and further by patterning a predetermined contact portion between a polyside gate and a diffusion layer. Thereafter, a P.sup.+ diffusion layer is formed by ion implantation with the use of the same photoresist mask. Further, a tungsten siliside layer is deposited all over the substrate. Or else, after the contact hole has been formed, the tungsten siliside layer is deposited, and then the P.sup.+ diffusion layer is formed by ion implantation. Alternatively, after the contact hole has been formed, a first ion implantation is made; and after the tungsten siliside layer has been deposited, a second ion implantation is made to form the P.sup.+ diffusion layer.

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.

Abstract: An amorphous silicon layer is used as an etch stop and is formed on the side wall of a first wiring layer having a predetermined wiring width and formed in a predetermined shape by patterning. A silicon oxide layer is covering the first wiring layer and the amorphous silicon layer, and a through-hole is formed in the silicon oxide layer so that a portion of the first wiring layer is exposed. The width of the through-hole is equal to or larger than the wiring width of the first wiring layer. A tungsten layer is filling the through-hole, and a second wiring layer connected to the tungsten layer is formed on the silicon oxide layer.