Patents by Inventor Fumitomo Watanabe
Fumitomo Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11742252Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.Type: GrantFiled: September 23, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 11335667Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: GrantFiled: February 3, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20220013421Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 11158554Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.Type: GrantFiled: October 18, 2019Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20210296216Abstract: A semiconductor device including a semiconductor chip, a plurality of leads and a sealing layer is disclosed. The lead includes a recess portion formed in the bottom surface at the outer side and a protruding portion formed in the top surface at the outer side. The protruding portion is formed to project from the top surface of the lead toward the sealing layer. A lead frame used in the semiconductor device and a method for manufacturing the semiconductor device are also disclosed.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Inventors: Toshitomo Fujiwara, Fumitomo Watanabe
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Publication number: 20210225805Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
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Patent number: 10998290Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.Type: GrantFiled: January 9, 2019Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
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Publication number: 20200321316Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: ApplicationFiled: February 3, 2020Publication date: October 8, 2020Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20200051882Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 10553566Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: GrantFiled: October 8, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 10453762Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.Type: GrantFiled: July 28, 2017Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20190148338Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
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Patent number: 10217719Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate formed from a molded material, a first semiconductor die at least partially embedded within the support substrate, a plurality of interconnects extending at least partially through the molded material, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second and third semiconductor dies.Type: GrantFiled: April 6, 2017Date of Patent: February 26, 2019Assignee: Micron Technology, Inc.Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
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Publication number: 20190043840Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: ApplicationFiled: October 8, 2018Publication date: February 7, 2019Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20190035706Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 10147705Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: GrantFiled: February 21, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Publication number: 20180294249Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate formed from a molded material, a first semiconductor die at least partially embedded within the support substrate, a plurality of interconnects extending at least partially through the molded material, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second and third semiconductor dies.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
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Publication number: 20180240782Abstract: Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Fumitomo Watanabe, Keiyo Kusanagi
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Patent number: 8810047Abstract: A semiconductor device includes: a substrate having first and second surfaces, the first surface comprising first and second regions; a first semiconductor chip covering the first region; a first seal covering the second region and the first semiconductor chip; and a second seal covering the second surface.Type: GrantFiled: October 13, 2009Date of Patent: August 19, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe
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Patent number: 8786102Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: October 10, 2013Date of Patent: July 22, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Masanori Yoshida, Fumitomo Watanabe