Abstract: A silicon carbide semiconductor device is manufactured without reducing an off-state breakdown voltage. The silicon carbide semiconductor device includes a second diffusion layer of a second conductivity type which is partially formed in a surface layer of a silicon carbide semiconductor layer of a first conductivity type, a third diffusion layer of the second conductivity type which is formed in at least part of a surface layer of the second diffusion layer, and a fourth diffusion layer of the first conductivity type which is partially formed in a surface layer of the third diffusion layer, and the third diffusion layer is formed to be shallower than the second diffusion layer, the fourth diffusion layer is formed inside the third diffusion layer in a cross-sectional view, and the third diffusion layer is asymmetric with respect to the second diffusion layer.

Abstract: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Abstract: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the n? epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Abstract: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the n? epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an n+ diffusion layer, an n? epitaxial layer, an n-type diffusion layer and an n+ diffusion layer. The n+ diffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The n+ diffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Abstract: A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an n+ diffusion layer, an n− epitaxial layer, an n-type diffusion layer and an n+ diffusion layer. The n+ diffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The n+ diffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Abstract: It is an object to provide a lateral transistor which enables a current gain rate to change less, even if it is used over a long time.

Abstract: Concerning a semiconductor device having a stacked capacitor including MOS and Poly-Poly capacitors, a semiconductor device structured without a need for excessive fine processing is provided. Also, a semiconductor device is provided which offers an increased capacitance density, while suppressing increases in manufacturing process and manufacturing cost. A highly-conductive diffusion layer doped with an N-type or P-type dopant is formed on a semiconductor substrate. A gate oxide film is formed in the surface of the highly-conductive diffusion layer by oxidizing the highly-conductive diffusion layer. A first polysilicon layer doped with an N-type or P-type dopant is formed on the gate oxide film. A dielectric layer is formed on the first polysilicon layer. A second polysilicon layer doped with an N-type or P-type dopant is formed on the dielectric layer.

Abstract: A semiconductor device with a surge protection circuit includes a surge protection circuit electrically connected to a signal input terminal and having an npn transistor and an npn transistor. The semiconductor device is configured such that the npn transistor is more susceptible to breakdown than the npn transistor, by implementing such a configuration that a narrowest region of a base of the npn transistor has a width different from that of a narrowest region of a base of the npn transistor. Thus, a semiconductor device with a surge protection circuit attaining a normal operation can be obtained.

Abstract: A base of a low breakdown voltage npn bipolar transistor has p+ diffusion layers. A field insulating layer is formed on the p+ diffusion layer located between the p+ diffusion layer and an emitter, while the p+ diffusion layer encloses the surface of the emitter and has a window part immediately under the emitter. Thus, a semiconductor device and a method of fabricating the same capable of suppressing dispersion of a current amplification factor hFE in a wafer plane of the low breakdown voltage transistor and fabricating the low breakdown voltage transistor and a high breakdown voltage transistor through simple steps are obtained.

Abstract: A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Abstract: A semiconductor device of the present invention comprises: an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.

Abstract: An npn transistor allowing the potential of each terminal to be easily set and superior in characteristics such as withstand-voltage performance and current amplification factor can be obtained. An n-type buried layer on a p-type substrate, a p-type buried layer on the n-type buried layer, n-type epitaxial layers covering the above layers, terminal regions on the surfaces of the layers, p-type outer-periphery layers encircling the terminal regions, and an encirclement layer encircling the layers are included, and p-type base regions and the p-type outer-periphery layer are continued to the p-type buried layer to separate a collector region from a p-type substrate and the n-type buried layer and the n-type encirclement layer are continued to separate the p-type buried layer, the p-type base region, and the p-type outer-periphery layer from the p-type substrate.

Abstract: A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

Abstract: The depletion N-channel transistor has a drain region formed in a circular shape and a gate region having a circular-shaped contour, disposed therein surrounding the drain region. A source region is disposed outside the gate region, surrounding the drain region and spaced a predetermined distance away from an element-isolating oxide film. For instance, a P+ diffused layer is formed outside the source region, and the P+ diffused layer spaces the source region a predetermined distance away from the element-isolating oxide film. In the P+ diffused layer is formed a contact hole 10 that is common to the P+ diffused layer and the source region, and the gate region and the drain region are disposed concentrically with each other.

Abstract: The method for manufacturing a semiconductor device includes the steps of: removing an oxide film in a region including a fuse region at the formation of an opening for the formation of a vertical interconnection in an oxide film serving as an upper insulating layer; and forming the vertical interconnection for electrically connecting interconnection layers below and above the oxide film and the interconnection layer placed on an upper side of the oxide film as one upper conductive layer at the same time.

Abstract: A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

Abstract: An npn transistor allowing the potential of each terminal to be easily set and superior in characteristics such as withstand-voltage performance and current amplification factor can be obtained.